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TAS2557YZR Datasheet(PDF) 10 Page - Texas Instruments |
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TAS2557YZR Datasheet(HTML) 10 Page - Texas Instruments |
10 / 110 page 10 TAS2557 SLASEC2 – NOVEMBER 2016 www.ti.com Product Folder Links: TAS2557 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated (1) All timing specifications are measured at characterization but not tested at final test. 7.8 I 2S/LJF/RJF Timing in Master Mode All specifications at TA = –40°C to 85°C, IOVDD data sheet limits, VIL and VIH applied, VOL and VOH measured at datasheet limits, lumped capacitive load of 20 pF on output pins unless otherwise noted. See Figure 3 (1) SYMBOL PARAMETER CONDITIONS IOVDD = 1.8 V IOVDD = 3.3 V UNIT MIN MAX MIN MAX td(WS) BCLK to WCLK delay 50% of BCLK to 50% of WCLK 35 25 ns td(DO-WS) WCLK to DOUT delay (For LJF Mode only) 50% of WCLK to 50% of DOUT 35 25 ns td(DO- BCLK) BCLK to DOUT delay 50% of BCLK to 50% of DOUT 35 25 ns ts(DI) DIN setup 8 8 ns th(DI) DIN hold 8 8 ns tr Rise time 10%-90% Rise Time 8 4 ns tf Fall time 90%-10% Fall Time 8 4 ns (1) All timing specifications are measured at characterization but not tested at final test. 7.9 I 2S/LJF/RJF Timing in Slave Mode All specifications at TA = –40°C to 85°C, IOVDD data sheet limits, VIL and VIH applied, VOL and VOH measured at datasheet limits, lumped capacitive load of 20 pF on output pins unless otherwise noted. See Figure 4 (1) SYMBOL PARAMETER CONDITIONS IOVDD = 1.8 V IOVDD = 3.3 V UNIT MIN MAX MIN MAX tH(BCLK) BCLK high period 40 30 ns tL(BCLK) BCLK low period 40 30 ns ts(WS) (WS) 8 8 ns th(WS) WCLK hold 8 8 ns td(DO-WS) WCLK to DOUT delay (For LJF Mode only) 50% of WCLK to 50% of DOUT 35 25 ns td(DO-BCLK) BCLK to DOUT delay 50% of BCLK to 50% of DOUT 35 25 ns ts(DI) DIN setup 8 8 ns th(DI) DIN hold 8 8 ns tr Rise time 10%-90% Rise Time 8 4 ns tf Fall time 90%-10% Fall Time 8 4 ns |
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