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932SQ426AGLFT Datasheet(PDF) 12 Page - Integrated Device Technology |
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932SQ426AGLFT Datasheet(HTML) 12 Page - Integrated Device Technology |
12 / 25 page 932SQ426 CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKING IDT® CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKING 12 932SQ426 REV C 022916 AC Electrical Characteristics - Differential Current Mode Outputs Electrical Characteristics - Phase Jitter Parameters TA = TCOM; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Duty Cycle tDC Measured differentially, PLL Mode 45 52 55 % 1 Skew, Output to Output tsk3SRC Across all SRC, NS-SAS outputs, VT = 50% 12 50 ps 1 Skew, Output to Output tsk3CPU Across all CPU outputs, VT = 50% 35 50 ps 1 CPU, SRC, NS_SAS outputs @100M 34 50 ps 1,3 DOT96 output 75 250 ps 1,3 1Guaranteed by design and characterization, not 100% tested in production. 2 I REF = VDD/(3xRR). For RR =412Ω (1%), IREF = 2.67mA. IOH = 6 x IREF and VOH = 0.7V @ ZO= 85Ω differential impedance. 3 Measured from differential waveform tjcyc-cyc Jitter, Cycle to cycle TA = 0 - 70°C; Supply Voltage VDD/VDDA = 3.3 V +/-5%, PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes tjphPCIeG1 PCIe Gen 1 16 86 ps (p-p) 1,2,3,6 PCIe Gen 2 Lo Band 10kHz < f < 1.5MHz 0.37 3 ps (rms) 1,2,6 PCIe Gen 2 High Band 1.5MHz < f < Nyquist (50MHz) 1.45 3.1 ps (rms) 1,2,6 tjphPCIeG3 PCIe Gen 3 (PLL BW of 2-4MHz, CDR = 10MHz) 0.35 1 ps (rms) 1,2,4,6 QPI & SMI (100MHz or 133MHz, 4.8Gb/s, 6.4Gb/s 12UI) 0.29 0.5 ps (rms) 1,5,6 QPI & SMI (100MHz, 8.0Gb/s, 12UI) 0.15 0.3 ps (rms) 1,5,6 QPI & SMI (100MHz, 9.6Gb/s, 12UI) 0.13 0.2 ps (rms) 1,5,6 tjphSAS12G SAS12G (Filtered REFCLK Jitter 20KHz to 20MHz.) 0.30 0.4 ps (rms) 1,7,8 tjphSAS12G SAS 12G 0.54 1.3 ps (rms) 1,5,8 1 Guaranteed by design and characterization, not 100% tested in production. 6 Applies to CPU, SRC and NS_SAS outputs 7 Intel calculation from raw phase noise data 8 Applies to NS_SAS and NS_SRC outputs only. 4 Subject to final radification by PCI SIG. 2 See http://www.pcisig.com for complete specs 3 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12. Phase Jitter tjphPCIeG2 tjphQPI_SMI 5 Calculated from Intel-supplied Clock Jitter Tool v 1.6.4 |
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