19-OUTPUT DB1900Z LOW-POWER DERIVATIVE W/85OHM TERMINATIONS 2

REVISION E 11/20/15

9ZXL1950 DATASHEET

Pin Configuration

Power Management Table

Power Connections

Functionality at Power-up (PLL mode)

PLL Operating Mode

Tri-level Input Thresholds

72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55

VDDA 1

54 DIF12#

GNDA 2

53 DIF12

^100M_133M# 3

52 VDDIO

^vHIBW_BYPM_LOBW# 4

51 GND

CKPWRGD_PD# 5

50 DIF11#

GND 6

49 DIF11

VDDR 7

48 DIF10#

DIF_IN 8

47 DIF10

DIF_IN# 9

46 GND

^SADR0_tri 10

45 VDD

SMBDAT 11

44 DIF9#

SMBCLK 12

43 DIF9

^SADR1_tri 13

42 DIF8#

FBOUT_NC# 14

41 DIF8

FBOUT_NC 15

40 VDDIO

GND 16

39 GND

DIF0 17

38 DIF7#

DIF0# 18

37 DIF7

19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

Note: Pins with ^ prefix have internal 120K pullup

Pins with v prefix have internal 120K pulldowm

Pins with ^v prefix have internal 120K pullup/pulldown (biased to VDD/2)

N/A 1530

9ZXL1950

(epad should be connected to GND and is

pin 73)

Control Bits

CKPWRGD_PD#

DIF_IN/

DIF_IN#

SMBus

EN bit

DIFx/

DIFx#

FBOUT_NC/

FB_OUT_NC#

0

X

X

Low/Low

Low/Low

OFF

0

Low/Low

Running

ON

1

Running

Running

ON

Inputs

PLL State

1

Running

Outputs

VDD

VDDIO

GND

1

2

Analog PLL

76

Analog Input

28, 45, 64

21, 33, 40,

52, 57, 69

16, 22, 27, 34,

39, 46, 51, 58,

63, 70, 73

DIF clocks

Pin Number

Description

100M_133M#

DIF_IN

(MHz)

DIFx

(MHz)

1

100.00

DIF_IN

0

133.33

DIF_IN

HiBW_BypM_LoBW# Byte0, bit (7:6)

Low ( PLL Low BW)

00

Mid (Bypass)

01

High (PLL High BW)

11

NOTE: PLL is off in Bypass mode

Level

Voltage

Low

<0.8V

Mid

1.2<Vin<1.8V

High

Vin > 2.2V