Electronic Components Datasheet Search |
|
9ZML1232BKLF Datasheet(PDF) 6 Page - Integrated Device Technology |
|
9ZML1232BKLF Datasheet(HTML) 6 Page - Integrated Device Technology |
6 / 19 page 9ZML1232 2:12 LOW POWER DIFFERENTIAL Z-BUFFER MUX FOR PCIE AND QPI/UPI IDT® 2:12 LOW POWER DIFFERENTIAL Z-BUFFER MUX FOR PCIE AND QPI/UPI 6 9ZML1232 REV E 112015 Electrical Characteristics–Input/Supply/Common Output Parameters TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, VDDIO = 1.05 to 3.3V +/-5%. See Test Loads for Loading Conditions PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Ambient Operating Temperature TCOM Commmercial range 0 25 70 °C 1 Input High Voltage VIH Single-ended inputs, except SMBus, low threshold and tri-level inputs 2VDD + 0.3 V 1 Input Low Voltage VIL Single-ended inputs, except SMBus, low threshold and tri-level inputs GND - 0.3 0.8 V 1 IIN Single-ended inputs, VIN = GND, VIN = VDD -5 -0.12 5 uA 1 IINP Single-ended inputs VIN = 0 V; Inputs with internal pull-up resistors VIN = VDD; Inputs with internal pull-down resistors -200 -0.02 200 uA 1 Input Frequency Fibyp VDD = 3.3 V, Bypass mode 33 150 MHz 2 Fipll VDD = 3.3 V, 100MHz PLL mode 90 100.00 110 MHz 2 Pin Inductance Lpin 7nH 1 CIN Logic Inputs, except DIF_IN 1.5 5 pF 1 CINDIF_IN DIF_IN differential clock inputs 1.5 2.7 pF 1,4 COUT Output pin capacitance 6 pF 1 Clk Stabilization TSTAB From VDD Power-Up and after input clock stabilization or de-assertion of PD# to 1st clock 1ms 1,2 Input SS Modulation Frequency fMODIN Allowable Frequency (Triangular Modulation) 30 33 kHz 1 OE# Latency tLATOE# DIF start after OE# assertion DIF stop after OE# deassertion 412 clocks 1 Tdrive_PD# tDRVPD DIF output enable after PD# de-assertion 300 us 1,3 Tfall tF Fall time of control inputs 5 ns 1,2 Trise tR Rise time of control inputs 5 ns 1,2 SMBus Input Low Voltage VILSMB 0.8 V 1 SMBus Input High Voltage VIHSMB 2.1 VDDSMB V1 SMBus Output Low Voltage VOLSMB @ IPULLUP 0.4 V 1 SMBus Sink Current IPULLUP @ VOL 4mA 1 Nominal Bus Voltage VDDSMB 3V to 5V +/- 10% 2.7 5.5 V 1 SCLK/SDATA Rise Time tRSMB (Max VIL - 0.15) to (Min VIH + 0.15) 1000 ns 1 SCLK/SDATA Fall Time tFSMB (Min VIH + 0.15) to (Max VIL - 0.15) 300 ns 1 SMBus Operating Frequency fMAXSMB Maximum SMBus operating frequency 400 kHz 1,5 1Guaranteed by design and characterization, not 100% tested in production. 2Control input must be monotonic from 20% to 80% of input swing. Input Current Capacitance 3Time from deassertion until outputs are >200 mV 4DIF_IN input 5The differential input clock must be running for the SMBus to be active |
Similar Part No. - 9ZML1232BKLF |
|
Similar Description - 9ZML1232BKLF |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |