9DBV0931AKILFT datasheet(8/18 Pages) IDT

Part #	9DBV0931AKILFT

Description	9-output 1.8V HCSL Fanout Buffer

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Manufacturer	IDT [Integrated Device Technology]

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9-OUTPUT 1.8V HCSL FANOUT BUFFER

8

REVISION D 03/28/16

9DBV0931 DATASHEET

Electrical Characteristics–DIF Low-Power HCSL Outputs

Electrical Characteristics–Current Consumption

TA = TCOM or TIND; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS NOTES

Scope averaging on, fast slew rate setting

2.3

3.4

4.3

V/ns

1,2,3

Scope averaging on, slow slew rate setting

1.4

2.2

3.1

V/ns

1,2,3

Slew rate matching

ΔTrf

Slew rate matching, Scope averaging on

5

20

%

1,2,4

Voltage High

VHIGH

660

774

850

7

Voltage Low

VLOW

-150

0

150

7

Max Voltage

Vmax

813

1150

7

Min Voltage

Vmin

-300

-55

7

Vswing

Scope averaging off

300

1548

mV

1,2

Crossing Voltage (abs)

Vcross_abs

Scope averaging off

250

404

550

mV

1,5

Crossing Voltage (var)

Δ-Vcross

Scope averaging off

12

140

mV

1,6

2 Measured from differential waveform

Slew rate

Trf

Statistical measurement on single-ended signal

using oscilloscope math function. (Scope

mV

5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising

edge (i.e. Clock rising and Clock# falling).

6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross

absolute) allowed. The intent is to limit Vcross induced modulation by setting

Δ-Vcross to be smaller than Vcross absolute.

7 660mV Vhigh is the minimum when VDDIO is >= 1.05V +/-5%. If VDDIO is < 1.05V +/-5%, the minimum Vhigh will be VDDIOmin -

250mV. For example for VDDIO = 0.9V +/-5%, VHIGHmin will be 860mV - 250mV = 610mV.

Measurement on single ended signal using

absolute value. (Scope averaging off)

mV

1Guaranteed by design and characterization, not 100% tested in production. C

L = 2pF with RS = 33Ω for Zo = 50Ω (100Ω differential

trace impedance).

3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around

differential 0V.

4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on

the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the

oscilloscope is to use for the edge rate calculations.

TA = TCOM or TIND; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

NOTES

IDDR

VDDR @100MHz

2.5

5

mA

1

IDDDIG

VDDIG, All outputs @100MHz

5.7

8

mA

1

IDDO

VDD1.8+VDDIO, All outputs @100MHz

36

45

mA

1

IDDRPD

VDDR, CKPWRGD_PD# = 0

0.4

1

mA

1, 2

IDDDIGPD

VDDDIG, CKPWRGD_PD# = 0

0.6

1.5

mA

1, 2

IDDOPD

VDD1.8+VDDIO, CKPWRGD_PD# = 0

0.0

0.1

mA

1, 2

1 Guaranteed by design and characterization, not 100% tested in production.

2 Input clock stopped.

Operating Supply Current

Powerdown Current

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