9DBV0831AKLFT datasheet(8/19 Pages) IDT

Part #	9DBV0831AKLFT

Description	8-output 1.8V PCIe Gen1/2/3 Zero-Delay/Fan-out Buffer

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Manufacturer	IDT [Integrated Device Technology]

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8-OUTPUT 1.8V PCIE GEN1/2/3 ZERO-DELAY/FAN-OUT BUFFER (ZDB/FOB) 8

REVISION H 04/28/16

9DBV0831 DATASHEET

Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating

Conditions

TA = TAMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS NOTES

Supply Voltage

VDDx

Supply voltage for core and analog

1.7

1.8

1.9

V

Output Supply Voltage

VDDIO

Supply voltage for Low Power HCSL Outputs

0.95

1.05

1.9

V

Commmercial range

0

25

70

°C

Industrial range

-40

25

85

°C

Input High Voltage

VIH

Single-ended inputs, except SMBus

0.75 VDD

VDD + 0.3

V

Input Mid Voltage

VIM

Single-ended tri-level inputs ('_tri' suffix)

0.4 VDD

0.6 VDD

V

Input Low Voltage

VIL

Single-ended inputs, except SMBus

-0.3

0.25 VDD

V

IIN

Single-ended inputs, VIN = GND, VIN = VDD

-5

5

uA

IINP

Single-ended inputs

VIN = 0 V; Inputs with internal pull-up resistors

VIN = VDD; Inputs with internal pull-down resistors

-200

200

uA

Fibyp

Bypass mode

1

200

MHz

2

Fipll

100MHz PLL mode

60

100.00

140

MHz

2

Fipll

125MHz PLL mode

75

125.00

175

MHz

2

Fipll

50MHz PLL mode

30

50.00

65

MHz

2

Pin Inductance

Lpin

7nH

1

CIN

Logic Inputs, except DIF_IN

1.5

5

pF

1

CINDIF_IN

DIF_IN differential clock inputs

1.5

2.7

pF

1,5

COUT

Output pin capacitance

6

pF

1

Clk Stabilization

TSTAB

From VDD Power-Up and after input clock

stabilization or de-assertion of PD# to 1st clock

1ms

1,2

Input SS Modulation

Frequency PCIe

fMODINPCIe

Allowable Frequency for PCIe Applications

(Triangular Modulation)

30

33

kHz

Input SS Modulation

Frequency non-PCIe

fMODIN

Allowable Frequency for non-PCIe Applications

(Triangular Modulation)

066

kHz

OE# Latency

tLATOE#

DIF start after OE# assertion

DIF stop after OE# deassertion

1

3

clocks

1,3

Tdrive_PD#

tDRVPD

DIF output enable after

PD# de-assertion

300

us

1,3

Tfall

tF

Fall time of single-ended control inputs

5

ns

2

Trise

tR

Rise time of single-ended control inputs

5

ns

2

SMBus Input Low Voltage

VILSMB

VDDSMB = 3.3V, see note 4 for VDDSMB < 3.3V

0.6

V

SMBus Input High Voltage

VIHSMB

VDDSMB = 3.3V, see note 5 for VDDSMB < 3.3V

2.1

3.6

V

4

SMBus Output Low Voltage

VOLSMB

@ IPULLUP

0.4

V

SMBus Sink Current

IPULLUP

@ VOL

4mA

Nominal Bus Voltage

VDDSMB

Bus Voltage

1.7

3.6

V

SCLK/SDATA Rise Time

tRSMB

(Max VIL - 0.15) to (Min VIH + 0.15)

1000

ns

1

SCLK/SDATA Fall Time

tFSMB

(Min VIH + 0.15) to (Max VIL - 0.15)

300

ns

1

SMBus Operating

Frequency

fMAXSMB

Maximum SMBus operating frequency

400

kHz

6

1Guaranteed by design and characterization, not 100% tested in production.

2Control input must be monotonic from 20% to 80% of input swing.

3Time from deassertion until outputs are >200 mV

5DIF_IN input

6The differential input clock must be running for the SMBus to be active

4 For V

DDSMB < 3.3V, VIHSMB >= 0.8xVDDSMB

Ambient Operating

Temperature

TAMB

Input Current

Input Frequency

Capacitance

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