PALCE20V8
Document #: 38-03026 Rev. **
Page 2 of 14
Shaded area contains preliminary information.
Functional Description (continued)
The PALCE20V8 features 8 product terms per output and 40
input terms into the AND array. The first product term in a mac-
rocell can be used either as an internal output enable control
or as a data product term.
There are a total of 18 architecture bits in the PALCE20V8
macrocell; two are global bits that apply to all macrocells and
16 that apply locally, two bits per macrocell. The architecture
bits determine whether the macrocell functions as a register or
combinatorial with inverting or noninverting output. The output
enable control can come from an external pin or internally from
a product term. The output can also be permanently enabled,
functioning as a dedicated output or permanently disabled,
functioning as a dedicated input. Feedback paths are select-
able from either the input/output pin associated with the mac-
rocell, the input/output pin associated with an adjacent pin, or
from the macrocell register itself.
Power-Up Reset
All registers in the PALCE20V8 power-up to a logic LOW for
predictable system initialization. For each register, the associ-
ated output pin will be HIGH due to active-LOW outputs.
Electronic Signature
An electronic signature word is provided in the PALCE20V8
that consists of 64 bits of programmable memory that can con-
tain user-defined data.
Security Bit
A security bit is provided that defeats the readback of the in-
ternal programmed pattern when the bit is programmed.
Low Power
The Cypress PALCE20V8 provides low-power operation
through the use of CMOS technology, and increased testability
with Flash reprogrammability.
Product Term Disable
Product Term Disable (PTD) fuses are included for each prod-
uct term. The PTD fuses allow each product term to be individ-
ually disabled.
Input and I/O Pin Pull-Ups
The PALCE20V8 input and I/O pins have built-in active
pull-ups that will float unused inputs and I/Os to an active
HIGH state (logical 1). All unused inputs and three-stated I/O
pins should be connected to another active input, VCC, or
Ground to improve noise immunity and reduce ICC.
Pin Configuration
PLCC/LCC
Top View
20V8–2
DIP/QSOP
Top View
25
24
23
22
21
20
19
5
6
7
8
9
10
11
121314 1516 1718
4 3 2
2827 26
1
1
2
3
4
5
6
7
8
9
10
11
14
15
16
20
19
18
17
21
24
23
22
12
13
OE/I11
I/O7
I/O0
I/O2
I/O1
I/O6
I/O5
I12
I/O3
VCC
I/O4
GND
I1
CLK/I0
I13
20V8–3
I2
I3
I4
I5
I6
I7
I8
I9
I10
I3
I4
I5
I6
I7
I8
NC
I/O2
I/O1
I/O6
I/O5
I/O3
I/O4
NC
Selection Guide
Generic Part Number
tPD ns
tS ns
tCO ns
ICC mA
Com’l/Ind
Mil
Com’l/Ind
Mil
Com’l/Ind
Mil
Com’l
Mil/Ind
PALCE20V8
−5
5
3
4
115
PALCE20V8
−7
7.5
7
5
115
PALCE20V8
−10
10
10
10
10
7
10
115
130
PALCE20V8
−15
15
15
12
12
10
12
90
130
PALCE20V8
−25
25
25
15
20
12
20
90
130
PALCE20V8L
−15
15
15
12
12
10
12
55
65
PALCE20V8L
−25
25
25
15
20
12
20
55
65
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