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KS8995MA Datasheet(PDF) 42 Page - Micrel Semiconductor |
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KS8995MA Datasheet(HTML) 42 Page - Micrel Semiconductor |
42 / 89 page Micrel, Inc. KS8995MA/FQ December 2012 42 M9999-121212-3.0 Pin # Pin Name PU/PD (1) Description (1) 86 SCONF1 Ipd Dual MII configuration pin. For the Switch MII, KSZ8995MA supports both MAC mode and PHY mode, KSZ8995FQ supports PHY mode only. Pins 91, 86, 87 Switch MII PHY [5] MII 000 Disable, Otri Disable, Otri 001 PHY Mode MII Disable, Otri 010 MAC Mode MII Disable, Otri 011 PHY Mode SNI Disable, Otri 100 Disable Disable 101 PHY Mode MII PHY Mode MII 110 MAC Mode MII PHY Mode MII 111 PHY Mode SNI PHY Mode MII 87 SCONF0 Ipd Dual MII configuration pin. 90 LED5-2 Ipu/O LED indicator 2. Strap option: Aging setup. See “Aging” section PU (default) = aging enable; PD = aging disable. 91 LED5-1 Ipu/O LED indicator 1. Strap option: PU (default): enable PHY[5] MII I/F. PD: tristate all PHY[5] MII output. See “Pin 86 SCONF1.” 113 PS1 Ipd Serial bus configuration pin. For this case, if the EEPROM is not present, the KS8995MA/FQ will start itself with the PS[1:0] =00 default register values . Pin Configuration Serial Bus Configuration PS[1:0]=00 I2C Master Mode for EEPROM PS[1:0]=01 Reserved PS[1:0]=10 SPI Slave Mode for CPU Interface PS[1:0]=11 Factory Test Mode (BIST) 114 PS0 Ipd Serial bus configuration pin. See “Pin 113.” 128 TEST2 NC NC for normal operation. Factory test pin. Note: 1. NC = No connect. Ipd = Input w/internal pull-down. Ipd/O = Input w/internal pull-down during reset, output pin otherwise. Otri = Output tristated. |
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