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PALCE20V8 Datasheet(PDF) 6 Page - Cypress Semiconductor

Part No. PALCE20V8
Description  Flash Erasable, Reprogrammable CMOS PAL Device
Download  14 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

PALCE20V8 Datasheet(HTML) 6 Page - Cypress Semiconductor

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PALCE20V8
Document #: 38-03026 Rev. **
Page 6 of 14
Commercial and Industrial Switching Characteristics[2]
20V8
−520V8−7
20V8
−10
20V8
−15
20V8
−25
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
tPD
Input to Output
Propagation Delay[8]
1
51
7.5
1
10
1
15
1
25
ns
tPZX
OE to Output Enable
56
10
15
20
ns
tPXZ
OE to Output Disable
56
10
15
20
ns
tEA
Input to Output
Enable Delay[7]
69
10
15
25
ns
tER
Input to Output
Disable Delay[7,9]
69
10
15
25
ns
tCO
Clock to Output Delay[8]
1
41
5
1
7
1
10
1
12
ns
tS
Input or Feedback
Set-Up Time
3
7
10
12
15
ns
tH
Input Hold Time
0
0
0
0
0
ns
tP
External Clock Period
(tCO + tS)
7
12
17
22
27
ns
tWH
Clock Width HIGH[7]
3
5
8
8
12
ns
tWL
Clock Width LOW[7]
3
5
8
8
12
ns
fMAX1
External Maximum
Frequency (1/(tCO + tS))
[7,10]
143
83
58
45.5
37
MHz
fMAX2
Data Path Maximum
Frequency
(1/(tWH + tWL))
[7, 11]
166.
6
100
62.5
62.5
41.6
MHz
fMAX3
Internal Feedback Maximum
Frequency (1/(tCF + tS))
[7,12]
166.
6
100
62.5
50
40
MHz
tCF
Register Clock to
Feedback Input[7, 13]
33
6
8
10
ns
tPR
Power-Up Reset Time[7]
1
1
1
1
1
µs
Shaded area contains preliminary information.
Notes:
8.
Min. times are tested initially and after any design or process changes that may affect these parameters.
9.
This parameter is measured as the time after OE pin or internal disable input disables or enables the output pin. This delay is measured to the point at which a previous
HIGH level has fallen to 0.5 volts below VOH min. or a previous LOW level has risen to 0.5 volts above VOL max.
10. This specification indicates the guaranteed maximum frequency at which a state machine configuration with external feedback can operate.
11.
This specification indicates the guaranteed maximum frequency at which the device can operate in data path mode.
12. This specification indicates the guaranteed maximum frequency at which a state machine configuration with internal only feedback can operate.
13. This parameter is calculated from the clock period at fMAX internal (1/fMAX3) as measured (see Note 7 above) minus tS.


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