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PALCE20V8 Datasheet(PDF) 4 Page - Cypress Semiconductor

Part No. PALCE20V8
Description  Flash Erasable, Reprogrammable CMOS PAL Device
Download  14 Pages
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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PALCE20V8 Datasheet(HTML) 4 Page - Cypress Semiconductor

 
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PALCE20V8
Document #: 38-03026 Rev. **
Page 4 of 14
Electrical Characteristics Over the Operating Range[2]
Parameter
Description
Test Conditions
Min.
Max.
Unit
VOH
Output HIGH Voltage
VCC = Min.,
VIN = VIH or VIL
IOH = −3.2 mA
Com’l
2.4
V
IOH = −2 mA
Mil/Ind
VOL
Output LOW Voltage
VCC = Min.,
VIN = VIH or VIL
IOL = 24 mA
Com’l
0.5
V
IOL = 12 mA
Mil/Ind
VIH
Input HIGH Level
Guaranteed Input Logical HIGH Voltage for All Inputs[3]
2.0
V
VIL
[4]
Input LOW Level
Guaranteed Input Logical LOW Voltage for All Inputs[3]
−0.5
0.8
V
IIH
Input or I/O HIGH Leakage
Current
3.5V < VIN < VCC
10
µA
IIL
[5]
Input or I/O LOW Leakage
Current
0V < VIN < VIN (Max.)
−100
µA
ISC
Output Short Circuit Current VCC = Max., VOUT = 0.5V
[6,7]
−30
−150
mA
ICC
Operating Power Supply
Current
VCC = Max.,
VIL = 0V, VIH = 3V,
Output Open,
f = 15 MHz
(counter)
5, 7, 10 ns
Com’l
115
mA
15, 25 ns
90
mA
15L, 25L ns
55
mA
10, 15, 25 ns
Mil/Ind
130
mA
15L, 25L ns
Mil/Ind
65
mA
Capacitance[7]
Parameter
Description
Test Conditions
Typ.
Unit
CIN
Input Capacitance
VIN = 2.0V @ f = 1 MHz
5
pF
COUT
Output Capacitance
VOUT = 2.0V @ f = 1 MHz
5
pF
Endurance Characteristics[7]
Parameter
Description
Test Conditions
Min.
Max.
Unit
N
Minimum Reprogramming Cycles
Normal Programming Conditions
100
Cycles
Notes:
2.
See the last page of this specification for Group A subgroup testing information.
3.
These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
4.
VIL (Min.) is equal to 3.0V for pulse durations less than 20 ns.
5.
The leakage current is due to the internal pull-up resistor on all pins.
6.
Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. VOUT = 0.5V has been chosen to avoid test problems
caused by tester ground degradation.
7.
Tested initially and after any design or process changes that may affect these parameters.


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