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MPC9350 Datasheet(PDF) 6 Page - Motorola, Inc

Part No. MPC9350
Description  LOW VOLTAGE PLL CLOCK DRIVER
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Maker  MOTOROLA [Motorola, Inc]
Homepage  http://www.freescale.com
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MPC9350 Datasheet(HTML) 6 Page - Motorola, Inc

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MPC9350
MOTOROLA
TIMING SOLUTIONS
6
APPLICATIONS INFORMATION
Programming the MPC9350
The MPC9350 clock driver outputs can be configured into
several divider modes, in addition the internal feedback of the
device allows for flexibility in establishing two input to output
frequency relationships. The output division settings establish
the output frequency relationship. The output divider of the
four output groups allows the user to configure the outputs into
1:1, 2:1, 4:1 and 4:2:1 frequency ratios. The use of even
dividers ensure that the output duty cycle is always 50%.
“Output Frequency Relationship FBSEL = 1, (VC0 = 32 * CLK)”
and “Output Frequency Relationship FBSEL = 0, (VC0 = 16 *
CLK)” illustrate the various output configurations. The tables
describes the outputs using the input clock frequency CLK as
a reference.
In addition, it must be ensured that the VCO will be stable
given the frequency of the outputs desired. The feedback
frequency should be used to situate the VCO into a frequency
range in which the PLL will be stable. The design of the PLL
supports output frequencies from 25 MHz to 200 MHz while
the VCO frequency range is specified from 200 MHz to 400
MHz and should not be exceeded for stable operation.
Output Frequency Relationshipa FBSEL = 1, (VC0 = 32 * CLK)
Inputs
Outputs
FSELA
FSELB
FSELC
FSELD
QA
QB
QC0, QC1
QD0-QD4
0
0
0
0
16 * CLK
8 * CLK
8 * CLK
8 * CLK
0
0
0
1
16 * CLK
8 * CLK
8 * CLK
4 * CLK
0
0
1
0
16 * CLK
8 * CLK
4 * CLK
8 * CLK
0
0
1
1
16 * CLK
8 * CLK
4 * CLK
4 * CLK
0
1
0
0
16 * CLK
4 * CLK
8 * CLK
8 * CLK
0
1
0
1
16 * CLK
4 * CLK
8 * CLK
4 * CLK
0
1
1
0
16 * CLK
4 * CLK
4 * CLK
8 * CLK
0
1
1
1
16 * CLK
4 * CLK
4 * CLK
4 * CLK
1
0
0
0
8 * CLK
8 * CLK
8 * CLK
8 * CLK
1
0
0
1
8 * CLK
8 * CLK
8 * CLK
4 * CLK
1
0
1
0
8 * CLK
8 * CLK
4 * CLK
8 * CLK
1
0
1
1
8 * CLK
8 * CLK
4 * CLK
4 * CLK
1
1
0
0
8 * CLK
4 * CLK
8 * CLK
8 * CLK
1
1
0
1
8 * CLK
4 * CLK
8 * CLK
4 * CLK
1
1
1
0
8 * CLK
4 * CLK
4 * CLK
8 * CLK
1
1
1
1
8 * CLK
4 * CLK
4 * CLK
4 * CLK
a.
Output frequency relationship with respect to input reference frequency CLK. Consult the MPC9351 datasheet more input to output
relationships in external feedback mode.
Output Frequency Relationshipa FBSEL = 0, (VC0 = 16 * CLK)
Inputs
Outputs
FSELA
FSELB
FSELC
FSELD
QA
QB
QC0, QC1
QD0-QD4
0
0
0
0
8 * CLK
4 * CLK
4 * CLK
4 * CLK
0
0
0
1
8 * CLK
4 * CLK
4 * CLK
2 * CLK
0
0
1
0
8 * CLK
4 * CLK
2 * CLK
4 * CLK
0
0
1
1
8 * CLK
4 * CLK
2 * CLK
2 * CLK
0
1
0
0
8 * CLK
2 * CLK
4 * CLK
4 * CLK
0
1
0
1
8 * CLK
2 * CLK
4 * CLK
2 * CLK
0
1
1
0
8 * CLK
2 * CLK
2 * CLK
4 * CLK
0
1
1
1
8 * CLK
2 * CLK
2 * CLK
2 * CLK
1
0
0
0
4 * CLK
4 * CLK
4 * CLK
4 * CLK
1
0
0
1
4 * CLK
4 * CLK
4 * CLK
2 * CLK
1
0
1
0
4 * CLK
4 * CLK
2 * CLK
4 * CLK
1
0
1
1
4 * CLK
4 * CLK
2 * CLK
2 * CLK
1
1
0
0
4 * CLK
2 * CLK
4 * CLK
4 * CLK
1
1
0
1
4 * CLK
2 * CLK
4 * CLK
2 * CLK
1
1
1
0
4 * CLK
2 * CLK
2 * CLK
4 * CLK
1
1
1
1
4 * CLK
2 * CLK
2 * CLK
2 * CLK
a.
Output frequency relationship with respect to input reference frequency CLK. Consult the MPC9351datasheet for more input to output
relationships in external feedback mode.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com


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