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LM1262 Datasheet(PDF) 5 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part No. LM1262
Description  200 MHz I2C Compatible RGB Video Amplifier System with OSD and DACs
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Maker  NSC [National Semiconductor (TI)]
Homepage  http://www.national.com

LM1262 Datasheet(HTML) 5 Page - National Semiconductor (TI)

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External Interface Signals Electrical Characteristics (Continued)
Unless otherwise noted: T
A = 25˚C, VCC = +5V, VIN = 0.7V, VABL =VCC,CL = 5 pF, Video Output = 2VP-P.
(Note 7)
(Note 6)
(Note 7)
H-Blank on
H-Blank Time Delay from Zero
Crossing Point of H Flyback
Rising Edge of the Flyback
H-Blank off
H-Blank Time Delay from Zero
Crossing Point of H Flyback
Falling Edge of the Flyback
In Threshold
In H-Blank Detection
Minimum — Insure Normal
Maximum — Should Not
Exceed in Normal Operation
Lowest Operating Horizontal
Frequency in Given Application
(Note 17)
In Flyback
Peak Current during Flyback
Period, Recommended Design
Operating Range for all
Horizontal Scan Frequencies,
Maximum Current Should Not
Exceed 2 mA (Note 17)
Note 1: Limits of Absolute Maximum Ratings indicate limits below which damage to the device must not occur.
Note 2: Limits of operating ratings indicate required boundaries of conditions for which the device is functional, but may not meet specific performance limits.
Note 3: All voltages are measured with respect to GND, unless otherwise specified.
Note 4: Human body model, 100 pF discharged through a 1.5 k
Ω resistor.
Note 5: Machine Model ESD test is covered by specification EIAJ IC-121-1981. A 200 pF cap is charged to the specified voltage, then discharged directly into the
IC with no external series resistor (resistance of discharge path must be under 50
Note 6: Typical specifications are specified at +25˚C and represent the most likely parametric norm.
Note 7: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 8: The supply current specified is the quiescent current for VCC with RL = . Load resistors are not required and are not used in the test circuit, therefore all
the supply current is used by the pre-amp.
Note 9: Linearity Error is the variation in step height of a 16 step staircase input signal waveform with 0.7 VP-P level at the input, subdivided into 16 equal steps,
with each step approximately 100 ns in width.
Note 10: Input from signal generator: tr,tf < 1 ns. Scope and generator response used for testing: tr = 1.1 ns, tf = 0.9 ns. Using the RSS technique the scope and
generator response have been removed from the output rise and fall times.
Note 11:
∆AV track is a measure of the ability of any two amplifiers to track each other and quantifies the matching of the three gain stages. It is the difference in
gain change between any two amplifiers with the contrast set to AV 1/2 and measured relative to the AV max condition. For example, at AV max the three amplifiers’
gains might be 12.1 dB, 11.9 dB, and 11.8 dB and change to 2.2 dB, 1.9 dB and 1.7 dB respectively for contrast set to AV 1/2. This yields a typical gain change of
10.0 dB with a tracking change of ±0.2 dB.
Note 12: ABL should provide smooth decrease in gain over the operational range of 0 dB to –6 dB
ABL = A(VABL =VABL Max Gain) - A(VABL =VABL Min Gain)
Beyond –6 dB the gain characteristics, linearity, pulse response, and/or behavior may depart from normal values.
Note 13: Adjust input frequency from 10 MHz (AV max reference level) to the −3 dB corner frequency (f−3 dB).
Note 14: Measure output levels of the other two undriven amplifiers relative to the driven amplifier to determine channel separation. Terminate the undriven amplifier
inputs to simulate generator loading. Repeat test at fIN = 10 MHz for Vsep 10 MHz.
Note 15: A minimum pulse width of 200 ns is guaranteed for a horizontal line of 15 kHz. This limit is guaranteed by design. If a lower line rate is used then a longer
clamp pulse may be required.
Note 16: The internal circuit detects the vertical blank only when this signal is present in the sandcastle input. There is typically an 800 nsec delay in detecting the
vertical blank signal. If only the horizontal clamp is present the vertical blank will not be activated. Rise and fall times of the sandcastle input signal should be 10 nsec
or faster.
Note 17: Limits met by matching the external resistor going to pin 24 to the H Flyback voltage.
Note 18: A 4.7 k
Ω resistor must be in series with pin 13 when this pin is the input for vertical blanking. When the LM1262 is first turned on the default condition for
pin 13 is for the DAC4 output. Under this condition pin 13 will be damaged by the vertical blanking input if a series resistor is not used.

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