PDI1394P25BY datasheet(9/42 Pages) PHILIPS

Part #	PDI1394P25BY

Description	1-port 400 Mbps physical layer interface

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Manufacturer	PHILIPS [NXP Semiconductors]

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Philips Semiconductors

Product data

PDI1394P25BY

1-port 400 Mbps physical layer interface

2002 Oct 11

9

9.0

RECOMMENDED OPERATING CONDITIONS

SYMBOL

PARAMETER

CONDITION

MIN

TYP

MAX

UNIT

SYMBOL

PARAMETER

CONDITION

MIN

TYP

MAX

UNIT

V

Supply voltage

Source power node

3.0

3.3

3.6

V

VDD

Supply voltage

Non-source power node

2.7 1

3.0

3.6

V

High-level input voltage, LREQ,

ISO = VDD, VDD >= 2.7 V

2.3

—

V

gg ,

,

CTL0, CTL1, D0-D7

ISO = VDD, VDD >= 3.0 V

2.6

—

V

VIH

High-level input voltage,

C/LKON2, PC0–PC2, ISO, PD

0.7 VDD

—

V

RESET

0.6 VDD

—

Low-level input voltage, LREQ,

CTL0, CTL1, D0–D7

ISO = VDD

—

0.7

V

VIL

Low-level input voltage, C/LKON2,

PC0–PC2, ISO, PD,

—

0.2 VDD

V

RESET

—

0.3 VDD

—

IO

Output current

TPBIAS outputs

–6

—

2.5

mA

V

Differential input voltage

TPA, TPB cable inputs, during data reception

118

—

260

mV

VID

g

amplitude

TPA, TPB cable inputs, during data arbitration

168

—

265

mV

V C

TPB common mode input voltage

Speed signaling off

or S100 speed

Source power node

1.165

—

2.515

V

VIC-100

TPB common-mode input voltage

or S100 s eed

signal

Non-source power node

1.165

—

2.0151

V

V C

TPB common mode input voltage

S200 speed signal

Source power node

0.935

—

2.515

V

VIC-200

TPB common-mode input voltage

S200 speed signal

Non-source power node

0.935

—

2.0151

V

V C

TPB common mode input voltage

S400 speed signal

Source power node

0.523

—

2.515

V

VIC-400

TPB common-mode input voltage

S400 speed signal

Non-source power node

0.523

—

2.0151

V

tPU

Power-up reset time

Set by capacitor between RESET pin and GND

2

—

ms

TPA, TPB cable inputs, S100 operation

—

1.08

ns

Receive input jitter

TPA, TPB cable inputs, S200 operation

—

0.5

ns

TPA, TPB cable inputs, S400 operation

—

0.315

ns

Between TPA and TPB cable inputs, S100

operation

—

0.8

ns

Receive input skew

Between TPA and TPB cable inputs, S200

operation

—

0.55

ns

Between TPA and TPB cable inputs, S400

operation

—

0.5

ns

fXTAL

Crystal or external clock

frequency

Crystal connected according to Figure 10 or

external clock input at pin XI

24.5735

24.576

24.5785

MHz

NOTES:

1. For a node that does not source power to the bus (see Section 4.2.2.2 in the IEEE 1394-1995 standard).

2. C/LKON is only an input when RESET = 0.

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