DS90LV110T

1 to 10 LVDS Data/Clock Distributor

General Description

DS90LV110 isa1to10 data/clock distributor utilizing LVDS

(Low Voltage Differential Signaling) technology for low

power, high speed operation. Data paths are fully differential

from input to output for low noise generation and low pulse

width distortion. The design allows connection of 1 input to

all 10 outputs. LVDS I/O enable high speed data transmis-

sion for point-to-point interconnects. This device can be used

as a high speed differential 1 to 10 signal distribution / fanout

replacing multi-drop bus applications for higher speed links

with improved signal quality. It can also be used for clock

distribution up to 400MHz.

The DS90LV110 accepts LVDS signal levels, LVPECL levels

directly or PECL with attenuation networks.

The LVDS outputs can be put into TRI-STATE by use of the

enable pin.

For more details, please refer to the Application Information

section of this datasheet.

Features

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Low jitter 800 Mbps fully differential data path

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145 ps (typ) of pk-pk jitter with PRBS = 2

pattern at 800 Mbps

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Single +3.3 V Supply

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Less than 413 mW (typ) total power dissipation

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Balanced output impedance

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Output channel-to-channel skew is 35ps (typ)

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Differential output voltage (V

100

Ω termination load.

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LVDS receiver inputs accept LVPECL signals

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Fast propagation delay of 2.8 ns (typ)

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28 lead TSSOP package

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Conforms to ANSI/TIA/EIA-644 LVDS standard

Connection Diagram

10133705

Order Number DS90LV110TMTC

See NS Package Number MTC28

Block Diagram

10133701

July 2001

© 2001 National Semiconductor Corporation

DS101337

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