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CDP68HC68P1 Datasheet(PDF) 6 Page - Intersil Corporation

Part No. CDP68HC68P1
Description  CMOS Serial 8-Bit Input/Output Port
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Maker  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
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CDP68HC68P1 Datasheet(HTML) 6 Page - Intersil Corporation

   
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feature and function (mask or data) of the byte immediately
following the control byte, the data byte (See Addressing the
Single Port I/O). Each bit of the data register may be
individually programmed as an input or output. A logic low in
a data direction bit programs that pin as an input, a logic high
makes it an output. A read operation of data register pins
programmed as inputs reflects the current logic level present
at the buffered port pins. A read operation of those data
register pins programmed as outputs indicates the last value
written to that location. At power-up, all port pins are
configured as unterminated inputs. Two chip identify pins are
used to allow up to 4 I/O ports to share the same chip enable
signal. The first two bits shifted in are compared with the
hardwired levels at the chip identify pins to enable the
selected I/O for serial data transfer. Note that when chip
enable becomes true, the compare flag is latched for all
devices sharing the same chip enable.
Compare Function
The value of a port pin (D0 - D7), configured as an input, is
compared with the corresponding bit value (DR0 - DR7)
stored in the Data Register. Pins configured as outputs are
assumed to have the same value as the corresponding bit
stored in the Data Register. The compare function is
programmed via C01 and C00 (CM1, CM0) of the Address
Byte. As shown in Table 1, the values for CM1 and CM0 will
sense one of four separate conditions.
The compare flag is set to one when the programmed
condition is satisfied. Otherwise, the flag is cleared to zero.
The compare flag is latched when the device is enabled (a
transition of CE from “High” to “Low”).
Data Format
During write operations, the data byte that follows the control
byte is normally the data word that is transferred to the data
or data direction register. Control bits 2 and 3 (DF0 and DF1)
change the interpretation of this data as shown in Table 2.
Note that one or more bits can be set or cleared in either
register without having to write to bits not requiring change.
TABLE 1.
CM1
CM0
CONDITION
0
0
At least one non-match
01
All match
1
0
All are non-match
1
1
At least one match
TABLE 2.
C03 DF1 C02 DF0
OPERATION
0
X
Data following the control word will be written to the selected register.
1
0
Data following the control word is a mask. Those bits which are a 1 will cause that register flip-flop to be cleared to 0. Those
which are a 0 will cause that register flip-flop to be unchanged.
1
1
Data following the control word is a mask. Those bits which are a 1 will cause that register flip-flop to be set to 1; those which
are a 0 will cause that register flip-flop to be unchanged.
TABLE 3. EXAMPLE
CONTROL
DATA
PREVIOUS
REGISTER VALUE
NEW
REGISTER VALUE
C07 C06 C05 1 0 X C01 C00
11110000
10101010
11110000
C07 C06 C05 1 1 1 C01 C00
11110000
10101010
11111010
C07 C06 C05 1 1 0 C01 C00
11110000
10101010
00001010
C07 C06 C05 1 1 X C01 C00
00000000
10101010
10101010
X = Don’t Care
FIGURE 6. CONTROL BYTE
CE
SCK
MISO
MOSI
OR
SCK
X
C07
C06
C05
C04
C03
C02
C01
C01
INPUT
Z
Z
Z
C07
C06
C05
C04
C03
*
OUTPUT
X = DON’T CARE
Z = HIGH IMPEDANCE
* = COMPARE FLAG
CDP68HC68P1


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