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NTD60N02R Datasheet(PDF) 1 Page - ON Semiconductor |
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NTD60N02R Datasheet(HTML) 1 Page - ON Semiconductor |
1 / 8 page © Semiconductor Components Industries, LLC, 2004 December, 2004 − Rev. 10 1 Publication Order Number: NTD60N02R/D NTD60N02R Power MOSFET 62 A, 24 V, N−Channel, DPAK Features • Planar HD3e Process for Fast Switching Performance • Low R DS(on) to Minimize Conduction Loss • Low C iss to Minimize Driver Loss • Low Gate Charge • Optimized for High Side Switching Requirements in High−Efficiency DC−DC Converters • Pb−Free Packages are Available MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating Symbol Value Unit Drain−to−Source Voltage VDSS 24 Vdc Gate−to−Source Voltage − Continuous VGS ±20 Vdc Thermal Resistance Junction−to−Case Total Power Dissipation @ TC = 25°C Drain Current Continuous @ TC = 25°C, Chip Continuous @ TC = 25°C, Limited by Package Continuous @ TA = 25°C, Limited by Wires RqJC PD ID ID ID 2.6 58 62 50 32 °C/W W A A A Thermal Resistance Junction−to−Ambient (Note 1) Total Power Dissipation @ TA = 25°C Drain Current − Continuous @ TA = 25°C RqJA PD ID 80 1.87 10.5 C/W W A Thermal Resistance Junction−to−Ambient (Note 2) Total Power Dissipation @ TA = 25°C Drain Current − Continuous @ TA = 25°C RqJA PD ID 120 1.25 8.5 °C/W W A Operating and Storage Temperature TJ, and Tstg − 55 to 175 °C Single Pulse Drain−to−Source Avalanche Energy − Starting TJ = 25°C (VDD = 50 Vdc, VGS = 10.0 Vdc, IL = 11 Apk, L = 1.0 mH, RG = 25 W) EAS 60 mJ Maximum Lead Temperature for Soldering Purposes, 1/8 ″ from case for 10 seconds TL 260 °C Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. When surface mounted to an FR4 board using 0.5 in sq drain pad size. 2. When surface mounted to an FR4 board using the minimum recommended pad size. MARKING DIAGRAM & PIN ASSIGNMENTS http://onsemi.com Y = Year WW = Work Week 60N02R = Device Code 24 V 8.4 m W @ 10 V RDS(on) TYP 62 A ID MAX V(BR)DSS CASE 369D DPAK (Straight Lead) STYLE 2 1 Gate 3 Source 2 Drain 4 Drain 1 Gate 3 Source 2 Drain 4 Drain 1 2 3 4 See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. ORDERING INFORMATION N−Channel D S G CASE 369AA DPAK (Surface Mount) STYLE 2 1 2 3 4 1 2 3 4 CASE 369C DPAK (Surface Mount) STYLE 2 |
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