REV. 0

–4–

AD7738

Parameter

Min

Typ

Max

Unit

Test Conditions/Comment

MASTER CLOCK RANGE

1

6.144

MHz

50

ns

SYNC Pulsewidth

500

ns

RESET Pulsewidth

READ OPERATION

0ns

CS Falling Edge to SCLK Falling Edge Setup Time

4

SCLK Falling Edge to Data Valid Delay

060

ns

080

ns

4, 5

CS Falling Edge to Data Valid Delay

060

ns

080

ns

50

ns

SCLK High Pulsewidth

50

ns

SCLK Low Pulsewidth

0ns

CS Rising Edge after SCLK Rising Edge Hold Time

6

10

80

ns

Bus Relinquish Time after SCLK Rising Edge

WRITE OPERATION

0ns

CS Falling Edge to SCLK Falling Edge Setup

30

ns

Data Valid to SCLK Rising Edge Setup Time

25

ns

Data Valid after SCLK Rising Edge Hold Time

50

ns

SCLK High Pulsewidth

50

ns

SCLK Low Pulsewidth

0ns

CS Rising Edge after SCLK Rising Edge Hold Time

NOTES

The measured number is then extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing

characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances.

Specifications are subject to change without notice.