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VSC7125QU Datasheet(PDF) 11 Page - Vitesse Semiconductor Corporation |
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VSC7125QU Datasheet(HTML) 11 Page - Vitesse Semiconductor Corporation |
11 / 16 page © VITESSE SEMICONDUCTOR CORPORATION Page 11 4/23/98 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC7125 1.0625 Gbits/sec Fibre Channel Transceiver G52121-0, Rev. 4.1 Package Pin Descriptions Figure 10: Pin Diagram Table 4: Pin Identification Pin # Name Description 2-4, 6-9, 11-13 T0:9 INPUTS - TTL 10-bit transmit character. Parallel data on this bus is clocked in on the rising edge of REFCLK. The data bit corresponding to T0 is transmitted first. 22 REFCLK INPUT - TTL This rising edge of this clock latches T0:9 into the input register. It also provides the reference clock, at one tenth the baud rate to the PLL. 62, 61 TX+, TX- OUTPUTS - Differential PECL (AC Coupling recommended) These pins output the serialized transmit data when EWRAP is LOW. When EWRAP is HIGH, TX+ is HIGH and TX- is LOW. 45-43, 41- 38, 36-34 R0:9 OUTPUTS - TTL 10-bit received character. Parallel data on this bus is clocked out on the rising edges of RCLK and RCLKN. R0 is the first bit received on RX+/RX-. T5 T4 VDDD T7 T8 T9 R6 R5 COMDET R4 VDDT R7 R8 T2 VDDD T3 R2 VSSD N/C VSST T6 N/C VSSD VSSD R9 R3 R1 R0 VSST VDDT T1 T0 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 63 61 59 57 55 53 51 49 33 35 37 39 41 43 45 47 (Top View) |
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