N64S818HA

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8

Page X

Word Y

Page X

Word Y+2

Page X

Word Y+1

Page X

Word 31

Page X

Word 0

Page X

Word 1

SI

SO

Data Words: sequential, at the end of the page the

address wraps back to the beginning of the page

16−bit address

Page address (X)

Word address (Y)

Figure 8. Page READ Sequence

Page X

Word Y

Page X

Word 31

Page X

Word Y+1

Page X

Word 0

Page X+1

Word Y

Page X+1

Word Y+1

SI

SO

16−bit address

Page address (X)

Word address (Y)

Data Words: sequential, at the end of the page the address wraps to the beginning

of the page and continues incrementing up to the starting word address. At that

time, the address increments to the next page and the burst continues.

. . .

Page X

Word 1

. . .

Page X

Word Y−1

Figure 9. Burst READ Sequence

WRITE Operations

The serial SRAM WRITE is selected by enabling CS low.

First, the 8−bit WRITE instruction is transmitted to the

device followed by the 16−bit address with the 3 MSBs

being don’t care. After the WRITE instruction and addresses

are sent, the data to be stored in memory is shifted in on the

SI pin.

If operating in page mode, after the initial word of data is

shifted in, additional data words can be written as long as the

address requested is sequential on the same page. Simply

write the data on SI pin and continue to provide clock pulses.

The internal address pointer is automatically incremented to

the next higher address on the page after each word of data

is written in. This can be continued for the entire page length

of 32 words long. At the end of the page, the addresses

pointer will be wrapped to the 0 word address within the

page and the operation can be continuously looped over the

32 words of the same page. The new data will replace data

already stored in the memory locations.

If operating in burst mode, after the initial word of data is

shifted in, additional data words can be written to the next

sequential memory locations by continuing to provide clock

pulses. The internal address pointer is automatically

incremented to the next higher address after each word of

data is read out. This can be continued for the entire array

and when the highest address is reached (1FFFh), the

address counter wraps to the address 0000h. This allows the

burst write cycle to be continued indefinitely. Again, the new

data will replace data already stored in the memory

locations.

All WRITE operations are terminated by pulling CS high.

CS

Instruction

SI

04

3

25

16

9

810

7

11

SCK

15 14 13 12

210

7

65

43

210

High−Z

16−bit address

Data In

SO

21

23

22

24

28 29 30 31

26 27

25

00

0

0

0

010

...

Figure 10. Word WRITE Sequence