N25S830HA

www.onsemi.com

10

WRITE Status Register Instruction (WRSR)

This instruction provides the ability to write the status

register and select among several operating modes. Several

of the register bits must be set to a low ‘0’ if any of the other

bits are written. The timing sequence to write to the status

register is shown below, followed by the organization of the

status register.

CS

Instruction

SI

04

3

25

16

9

810

711

SCK

7

654

3

21

0

High−Z

Status Register Data In

SO

00

0

00

1

0

12

13

14

15

0

Figure 14. WRITE Status Register Sequence

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Hold Function

0 = Hold (Default)

1 = No Hold

Reserved

Must = 0

Reserved

Must = 0

Mode

0 0 = Word Mode (Default)

1 0 = Page Mode

0 1 = Burst Mode

1 1 = Reserved

Figure 15. Status Register

READ Status Register Instruction (RDSR)

This instruction provides the ability to read the Status register. The register may be read at any time by performing the

following timing sequence.

CS

Instruction

SI

04

3

25

16

9

810

711

SCK

7

65

43

21

0

High−Z

Status Register Data Out

SO

00

0

00

1

0

12

13

14

15

1

Figure 16. READ Status Register Instruction (RDSR)

Power−Up State

The serial SRAM enters a know state at power−up time. The device is in low−power standby state with CS = 1. A low level

on CS is required to enter an active state.