8-O/P 1.8V PCIE GEN 1/2/3 CLOCK GENERATOR

8

OCTOBER 18, 2016

9FGV0831 DATASHEET

Electrical Characteristics–DIF Low Power HCSL Outputs

Electrical Characteristics–DIF Output Phase Jitter Parameters

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS NOTES

Scope averaging on fast setting

1.8

2.7

4.4

V/ns

1,2,3

Scope averaging on slow setting

1.4

2.1

3.4

V/ns

1,2,3

Slew rate matching

ΔTrf

Slew rate matching, Scope averaging on

4

20

%

1,2,4

Voltage High

660

793

850

7

Voltage Low

-150

16

150

7

Max Voltage

Vmax

831

1150

7

Min Voltage

Vmin

-300

-95

7

Vswing

Vswing

Scope averaging off

300

1555

mV

1,2,7

Crossing Voltage (abs)

Vcross_abs

Scope averaging off

250

429

550

mV

1,5,7

Crossing Voltage (var)

Δ-Vcross

Scope averaging off

12

140

mV

1,6,7

Measurement on single ended signal using

absolute value. (Scope averaging off)

mV

Slew rate

Trf

Statistical measurement on single-ended signal

using oscilloscope math function. (Scope

averaging on)

mV

differential 0V.

average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the

oscilloscope is to use for the edge rate calculations.

edge (i.e. Clock rising and Clock# falling).

absolute) allowed. The intent is to limit Vcross induced modulation by setting

Δ-Vcross to be smaller than Vcross absolute.

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

IND.

LIMIT

UNITS

Notes

PCIe Gen 1

25

35

86

ps (p-p)

1,2,3

PCIe Gen 2 Lo Band

10kHz < f < 1.5MHz

0.9

1.1

3

ps

(rms)

1,2,3

PCIe Gen 2 High Band

1.5MHz < f < Nyquist (50MHz)

1.6

1.9

3.1

ps

(rms)

1,2,3

PCIe Gen 3 Common Clock Architecture

(PLL BW of 2-4 or 2-5MHz, CDR = 10MHz)

0.36

0.5

1

ps

(rms)

1,2,3

S

PCIe Gen 3 Separate Reference No Spread (SRnS)

(PLL BW of 2-4 or 2-5MHz, CDR = 10MHz)

0.36

0.5

0.7

ps

(rms)

1,2,3

Phase Jitter, PLL Mode

4