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9FGU0841AKLIFT Datasheet(PDF) 2 Page - Integrated Device Technology |
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9FGU0841AKLIFT Datasheet(HTML) 2 Page - Integrated Device Technology |
2 / 16 page 8-OUTPUT 1.5V PCIE GEN1-2-3 CLOCK GENERATOR W/ZO=100OHMS 2 OCTOBER 18, 2016 9FGU0841 DATASHEET Pin Configuration Power Management Table SMBus Address Selection Table Power Connections 48 47 46 45 44 43 42 41 40 39 38 37 vSS_EN_tri 1 36 DIF5# GNDXTAL 2 35 DIF5 XIN/CLKIN_25 3 34 vOE4# X2 4 33 DIF4# VDDXTAL1.5 5 32 DIF4 VDDREF1.5 6 31 VDDIO vSADR/REF1.5 7 30 VDDA1.5 GNDREF 8 29 GNDA GNDDIG 9 28 vOE3# SCLK_3.3 10 27 DIF3# SDATA_3.3 11 26 DIF3 VDDDIG1.512 25vOE2# 13 14 15 16 17 18 19 20 21 22 23 24 vv prefix indicates internal 60KOhm pull down resistor v prefix indicates internal 120KOhm pull down resistor ^ prefix indicates internal 120KOhm pull up resistor 48-pin MLF, 6x6 mm, 0.4mm pitch 9FGU0841 OEx# True O/P Comp. O/P 0 X X Low Low Hi-Z1 1 1 0 Running Running Running 1 0 1 Low Low Low REF CKPWRGD_PD# SMBus OE bit DIFx 1. REF is Hi-Z until the 1st assertion of CKPWRGD_PD# high. After this, when CKPWRGD_PD# is low, REF is Low. SADR Address 0 1101000 1 1101010 State of SADR on first application of CKPWRGD_PD# + Read/Write Bit x x Pin Number VDD VDDIO GND 5 2 XTAL OSC 68 REF Power 12 9 Digital (dirty) Power 20,38 13,21,31,39, 47 22,29,40 DIF outputs 30 29 PLL Analog Description |
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