8-O/P 1.5V PCIE GEN 1-2-3 CLOCK GENERATOR

4

OCTOBER 18, 2016

9FGU0831 DATASHEET

Pin Descriptions (cont.)

PIN #

PIN NAME

TYPE

DESCRIPTION

40

GND

GND

Ground pin.

41

DIF6

OUT

Differential true clock output

42

DIF6#

OUT

Differential Complementary clock output

43

vOE6#

IN

Active low input for enabling DIF pair 6. This pin has an internal pull-down.

1 =disable outputs, 0 = enable outputs

44

DIF7

OUT

Differential true clock output

45

DIF7#

OUT

Differential Complementary clock output

46

vOE7#

IN

Active low input for enabling DIF pair 7. This pin has an internal pull-down.

1 =disable outputs, 0 = enable outputs

47

VDDIO

PWR

Power supply for differential outputs

48

^CKPWRGD_PD#

IN

Input notifies device to sample latched inputs and start up on first high

assertion. Low enters Power Down Mode, subsequent high assertions exit

Power Down Mode. This pin has internal pull-up resistor.