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9FGU0431 Datasheet(PDF) 2 Page - Integrated Device Technology |
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9FGU0431 Datasheet(HTML) 2 Page - Integrated Device Technology |
2 / 15 page 4 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR 2 OCTOBER 18, 2016 9FGU0431 DATASHEET Pin Configuration SMBus Address Selection Table Power Management Table Power Connections 32 31 30 29 28 27 26 25 GNDXTAL 1 24 vOE2# XIN/CLKIN_25 2 23 DIF2# X2 3 22 DIF2 VDDXTAL1.5 4 21 VDDA1.5 VDDREF1.5 5 20 GNDA vSADR/REF1.5 6 19 DIF1# GNDREF 7 18 DIF1 GNDDIG 817 vOE1# 9 10111213 141516 32-pin VFQFPN, 5x5 mm, 0.5mm pitch v prefix indicates internal 120KOhm pull down resistor 9FGU0431 ^ prefix indicates internal 120KOhm pull up resistor SADR Address 0 1101000 1 1101010 State of SADR on first application of CKPWRGD_PD# + Read/Write Bit x x OEx# True O/P Comp. O/P 0 X X Low Low Hi-Z1 1 1 0 Running Running Running 1 0 1 Low Low Low REF CKPWRGD_PD# SMBus OE bit DIFx 1. REF is Hi-Z until the 1st assertion of CKPWRGD_PD# high. After this, when CKPWRG_PD# is low, REF is Low. Pin Number VDD GND 41 57 98, 30 16, 25 15, 26 21 20 PLL Analog REF Output Description XTAL Analog Digital Power DIF outputs |
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