PI74ALVCH1622601

18-BIT UNIVERSAL BUS TRANSCEIVER

2

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PS8115B

02/03/98

Pin Name

Description

CLKEN

Clock Enable Input (Active LOW)

OE

Output Enable Input (Active LOW)

LE

Latch Enable (Active HIGH)

CLK

Clock Input (Active HIGH)

Ax

Data I/O

Bx

Data I/O

GND

Ground

Power

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

25

26

27

28

32

31

30

29

Product Pin Description

Notes:

1. H = High Signal Level

L = Low Signal Level

Z = High Impedance

↑ = LOW-to-HIGH Transition

† A-to-B data flow is shown:

B-to-A flow is similar but uses OEBA, LEBA,

CLKBA, and CLKENBA.

‡ Output level before the indicated steady-state input

conditions were established.

§ Output level before the indicated steady-state input

conditions were established, provided that CLKAB is

LOW before LEAB goes LOW.

Product Pin Configuration

56-PIN

A-56

V-56

s

t

u

p

n

I

t

u

p

t

u

O

B

B

A

N

E

K

L

CB

A

E

OB

A

E

LB

A

K

L

CA

XH

X

X

X

Z

XL

H

X

L

L

XL

H

S

H

H

HL

L

X

X

HL

L

X

X

LL

L

­

LL

LL

L

­

HH

LL

L

L

X

LL

L

H

X

OEAB

LEAB

A1

GND

A2

A3

VCC

A4

A5

A6

GND

A7

A8

A9

A10

A11

A12

GND

A13

A14

A15

VCC

A16

A17

GND

A18

OEBA

LEBA

CLKENAB

CLKAB

B1

GND

B2

B3

VCC

B4

B5

B6

GND

B7

B8

B9

B10

B11

B12

GND

B13

B14

B15

VCC

B16

B17

GND

B18

CLKBA

CLKENBA