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9FGL02 Datasheet(PDF) 12 Page - Integrated Device Technology |
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9FGL02 Datasheet(HTML) 12 Page - Integrated Device Technology |
12 / 19 page 2-OUTPUT 3.3V PCIE CLOCK GENERATOR 12 OCTOBER 18, 2016 9FGL02 DATASHEET SMBus Table: Revision and Vendor ID Register Byte 5 Name Control Function Type 0 1 Default Bit 7 RID3 R 0 Bit 6 RID2 R 0 Bit 5 RID1 R 0 Bit 4 RID0 R 1 Bit 3 VID3 R 0 Bit 2 VID2 R 0 Bit 1 VID1 R 0 Bit 0 VID0 R 1 SMBus Table: Device Type/Device ID Byte 6 Name Control Function Type 0 1 Default Bit 7 Device Type1 R 0 Bit 6 Device Type0 R 0 Bit 5 Device ID5 R 0 Bit 4 Device ID4 R 0 Bit 3 Device ID3 R 0 Bit 2 Device ID2 R 0 Bit 1 Device ID1 R 1 Bit 0 Device ID0 R 0 SMBus Table: Byte Count Register Byte 7 Name Control Function Type 0 1 Default Bit 7 X Bit 6 X Bit 5 X Bit 4 BC4 RW 0 Bit 3 BC3 RW 1 Bit 2 BC2 RW 0 Bit 1 BC1 RW 0 Bit 0 BC0 RW 0 Bytes 8 and 9 are Reserved SMBus Table: PLL MN Enable, PD_Restore Byte 10 Name Control Function Type 0 1 Default Bit 7 Reserved Reserve bit, leave at default RW Reserved Reserved 0 Bit 6 Power-Down (PD) Restore Restore Default Config. In PD RW Clear Config in PD Keep Config in PD 1 Bit 5 X Bit 4 X Bit 3 X Bit 2 X Bit 1 X Bit 0 X Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Byte Count Programming Writing to this register will configure how many bytes will be read back, default is = 8 bytes. Reserved VENDOR ID 0001 = IDT Device Type 00 = FGx, 01 = DBx, 10 = DMx, 11= DBx w/oPLL Device ID 00010 binary or 02 hex Revision ID B rev = 0001 |
Similar Part No. - 9FGL02_16 |
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Similar Description - 9FGL02_16 |
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