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8T73S208 Datasheet(PDF) 15 Page - Integrated Device Technology |
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8T73S208 Datasheet(HTML) 15 Page - Integrated Device Technology |
15 / 22 page 15 ©2016 Integrated Device Technology, Inc. Revision D, June 15, 2016 8T73S208 Datasheet Power Considerations This section provides information on power dissipation and junction temperature for the 8T73S208. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the 8T73S208 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 95mA = 329.175mW • Power (outputs)MAX = 36.3mW/Loaded Output pair If all outputs are loaded, the total power is 8 * 36.3mW = 290.4mW • Power Dissipation for internal termination RT (Assuming VIN = 0.15V and VCMR = 3.225V VIH = 3.3V and VIL = 3.15V; and external 50 is connected from VT pin to VEE.) Power (RT)MAX = 46.5mW Total Power_MAX = (3.465V, with all outputs switching) = 329.175mW + 290.4mW + 46.5mW = 666.08mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 42.7°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.666W * 42.7°C/W = 113.4°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 6. Thermal Resistance JA for 32 Lead VFQFN, Forced Convection JA vs. Air Flow Meters per Second 01 2.5 Multi-Layer PCB, JEDEC Standard Test Boards 42.7°C/W 37.3°C/W 33.5°C/W |
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Similar Description - 8T73S208_16 |
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