4

SP5511

FUNCTIONAL DESCRIPTION

Clock are fed in on the SDA and SCL lines respectively as

accept new data (write mode) or send data (read mode). The

Tables in Fig. 3 illustrate the format of the data. The device

can be programmed to respond to several addresses, which

system. Table

4 shows how the address is selected by

applying a voltage to P3. The address input circuit is shown

in Fig.6.The LSB of the address Byte (R/W) sets the device

into read mode if it is high and write mode if it is low. When

the SP5511 receives a correct address Byte it pulls the SDA

line low during the acknowledge period and during following

acknowledge periods after further data Bytes are programmed.

When the SP5511 is programmed into the read mode the

controlling device accepting the data must pull down the SDA

line during the following acknowledge period to read another

status Byte.

WRITE MODE (FREQUENCY SYNTHESIS)

When the device is in the write mode Bytes 213 select the

synthesised frequency while Bytes 415 select the output port

states and charge pump information.

Once the correct address is received and acknowledged,

the first Bit of the next Byte determines whether that Byte is

interpreted as Byte 2 or 4, a logic 0 for frequency information

and a logic 1 for charge pump and output port information.

Additional data Bytes can be entered without the need to re-

This allows a smooth frequency sweep for fine tuning or AFC

purposes.

If the transmission of data is stopped mid-byte (i.e., by

another device on the bus) then the previously programmed

byte is maintained.

Frequency data from Bytes 2 and 3 is stored in a 15-bit shift

register and is used to control the division ratio of the 15-bit

programmable divider which is preceded by a divide-by-8

prescaler and amplifier to give excellent sensitivity at the local

oscillator input; see Fig 5. The input impedance is shown in

Figs. 7 and 8.

The programmed frequency can be calculated by multiply-

ing the programmed division ratio by 8 times the comparison

When frequency data is entered, the phase comparator,

via the charge pump and varactor drive amplifier, adjusts the

local oscillator control voltage until the output of the program-

mable divider is frequency and phase locked to the comparison

frequency.

The reference frequency may be generated by an external

source capacitively coupled into pin 2 or provided by an on-

chip 4MHz crystal controlled oscillator.

Note that the comparison frequency is 7·8125kHz when a

4MHz reference is used.

Bit 2 of Byte 4 of the programming data (CP) controls the

current in the charge pump circuit, a logic 1 for 6170

µA and

a logic 0 for 650

µA, allowing compensation for the variable

tuning slope of the tuner and also to enable fast channel

changes over the full band. Bit 4 of Byte 4 (T0) disables the

charge pump if set to a logic 1. Bit 8 of Byte 4 (OS) switches

the charge pump drive amplifier’s output off when it is set to

a logic 1. Bit 3 of Byte 4 (T1) selects a test mode where the

phase comparator inputs are available on P6 and P7, a logic

Byte 5 programs the output ports P0-P7, a logic 0 for a high

impedance output, logic 1 for low impedance (on).

READ MODE

When the device is in the read mode the status data read

from the device on the SDA line takes the form shown in Table

2.

Bit 1 (POR) is the power on reset indicator and is set to a

logic 1 if the power supply to the device has dropped below a

nominal 3V and the programmed information lost (e.g., when

the device is initially turned on). The POR is set to 0 when the

read sequence is terminated by a stop command. The outputs

are all set to high impedance when the device is initially

powered up. Bit 2 (FL) indicates whether the device is phase

locked, a logic 1 is present if the device is locked and a logic

0 if the device is unlocked.

Bits 3, 4 and 5 (I2, I1, I0) show the status of the I/O Ports

P7, P5 and P4 respectively. A logic 0 indicates a low level and

a logic 1 a high level. If the ports are to be used as inputs they

should be programmed to a high impedance state (logic1).

These inputs will then respond to data complying with stand-

ard TTL voltage levels. Bits 6, 7 and 8 (A2,A1,A0) combine to

give the output of the 5-level ADC.

The 5-level ADC can be used to feed AFC information to

the microprocessor from the IF section of the television, as

illustrated in Fig. 4.