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CS8416-IS Datasheet(PDF) 37 Page - Cirrus Logic |
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CS8416-IS Datasheet(HTML) 37 Page - Cirrus Logic |
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37 / 48 page  CS8416 DS578PP2 37 10 HARDWARE MODE The CS8416 has a hardware mode which allows using the device without a microcontroller. Hardware mode is selected by connecting the 47K pull-up/down resistor on the SDOUT pin to ground. Various pins change function in hardware mode, described in the hardware mode pin definition section (Section 11). Hardware mode data flow is shown in Figure 13. Audio data is input through the AES3/SPDIF receiver, and routed to the serial audio output port. The decoded C and U bits are also output, clocked at both edges of OLRCK (master mode only, see Figure 9). An error in the incoming audio stream will be indicated on the NV/RERR. This pin can be configured in one of two ways. If RERR is chosen by pulling NV/RERR to ground, the previous audio sample is held and passed to the serial audio output port if the validity bit is high, or a parity, bi-phase, confidence or PLL lock error occurs during the current sample. If NVERR is chosen by pulling NV/RERR to VL+, only par- ity, bi-phase, confidence or PLL lock error cause the previous audio sample to be held. 10.1 Serial Audio Port Formats In hardware mode, only a limited number of alternative serial audio port formats are available. Table 4 de- fines the equivalent software mode bit settings for each format. The start-up options, shown in Table 4, allow choice of the serial audio output port as a master or slave, and the serial audio port format. NV/RERR Power supply pins (VA+, VD+, VL+, AGND, DGND, the reset pin (RST) and the PLL filter pin (FILT) are omitted from the diagram. Please refer to the Typical Connection Diagram for connection details. RXP1 4:2 MUX RXP2 RXP3 RXP0 96kHz RMCK RXSEL[1:0] TXSEL[1:0] AUDIO RCBL RXN AES3 Rx & Decoder OMCK TX OLRCK OSCLK SDOUT C U De-emphasis Filter Serial Audio Output Figure 13. Hardware Mode Data Flow |
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