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9DBL0851BKILFT Datasheet(PDF) 3 Page - Integrated Device Technology

Part # 9DBL0851BKILFT
Description  8-output 3.3V PCIe Zero-Delay Buffer
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

9DBL0851BKILFT Datasheet(HTML) 3 Page - Integrated Device Technology

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REVISION D 08/16/16
3
8-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER
9DBL08 DATASHEET
Pin Descriptions
PIN #
PIN NAME
TYPE
DESCRIPTION
1
vSADR_tri
LATCHED
IN
Tri-level latch to select SMBus Address. See SMBus Address Selection Table.
2
^vHIBW_BYPM_LOBW#
LATCHED
IN
Trilevel input to select High BW, Bypass or Low BW mode. This pin is biased
to VDD/2 (Bypass mode) with internal pull up/pull down resistors. See PLL
Operating Mode Table for Details.
3
FB_DNC
DNC
True clock of differential feedback. The feedback output and feedback input are
connected internally on this pin. Do not connect anything to this pin.
4
FB_DNC#
DNC
Complement clock of differential feedback. The feedback output and feedback
input are connected internally on this pin. Do not connect anything to this pin.
5
VDDR3.3
PWR
3.3V power for differential input clock (receiver). This VDD should be treated as
an Analog power rail and filtered appropriately.
6
CLK_IN
IN
True Input for differential reference clock.
7
CLK_IN#
IN
Complementary Input for differential reference clock.
8
GNDR
GND
Analog Ground pin for the differential input (receiver)
9
GNDDIG
GND
Ground pin for digital circuitry
10
SCLK_3.3
IN
Clock pin of SMBus circuitry, 3.3V tolerant.
11
SDATA_3.3
I/O
Data pin for SMBus circuitry, 3.3V tolerant.
12
VDDDIG3.3
PWR
3.3V digital power (dirty power)
13
VDDIO
PWR
Power supply for differential outputs
14
vOE0#
IN
Active low input for enabling output 0. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
15
DIF0
OUT
Differential true clock output
16
DIF0#
OUT
Differential Complementary clock output
17
vOE1#
IN
Active low input for enabling output 1. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
18
DIF1
OUT
Differential true clock output
19
DIF1#
OUT
Differential Complementary clock output
20
VDD3.3
PWR
Power supply, nominal 3.3V
21
VDDIO
PWR
Power supply for differential outputs
22
GND
GND
Ground pin.
23
DIF2
OUT
Differential true clock output
24
DIF2#
OUT
Differential Complementary clock output
25
vOE2#
IN
Active low input for enabling output 2. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
26
DIF3
OUT
Differential true clock output
27
DIF3#
OUT
Differential Complementary clock output
28
vOE3#
IN
Active low input for enabling output 3. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
29
GNDA
GND
Ground pin for the PLL core.
30
VDDA3.3
PWR
3.3V power for the PLL core.
31
VDDIO
PWR
Power supply for differential outputs
32
DIF4
OUT
Differential true clock output
33
DIF4#
OUT
Differential Complementary clock output
34
vOE4#
IN
Active low input for enabling output 4. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
35
DIF5
OUT
Differential true clock output
36
DIF5#
OUT
Differential Complementary clock output
37
vOE5#
IN
Active low input for enabling output 5. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
38
VDD3.3
PWR
Power supply, nominal 3.3V
39
VDDIO
PWR
Power supply for differential outputs


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