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NL3S22S Datasheet(PDF) 5 Page - ON Semiconductor

Part # NL3S22S
Description  USB 2.0 Audio Switch
Download  9 Pages
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

NL3S22S Datasheet(HTML) 5 Page - ON Semiconductor

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NL3S22S
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5
AC ELECTRICAL CHARACTERISTICS (Typical values are at VCC = +3.6 V and TA = +25 ⁰C)
Symbol
Parameter
Test Conditions
VCC (V)
−40 ⁰C to 85 ⁰C
Unit
Min
Typ
Max
AUDIO SWITCH (AUDP/AUDN e D+/D−)
THD
Audio THD
f = 20 Hz to 20 kHz, VIS = 0.4 VRMS,
DC Bias = 0 V, RL = 16 W
2.7 – 5.5
0.002
%
PSRR
Power Supply Ripple
Rejection
From VCC unto AUDP/AUDN,
f = 217 Hz, RL = 16 W
2.7 – 5.5
118
dB
DATA SWITCH (HDP/HDN e D+/D−)
CON
Equivalent
ON−Capacitance
Switch ON, f = 1 MHz
3.6
4.84
pF
COFF
Equivalent
OFF−Capacitance
Switch OFF, f = 1 MHz
3.6
2.06
pF
DIL
Differential Insertion
Loss
f = 10 MHz
2.7 – 5.5
−0.42
dB
f = 800 MHz
2.7 – 5.5
−1.89
f = 1.1 GHz
2.7 – 5.5
−3.01
DISO
Differential Off−Isolation
f = 10 MHz
2.7 – 5.5
−60
dB
f = 800 MHz
2.7 – 5.5
−15
f = 1.1 GHz
2.7 – 5.5
−15
DCTK
Differential Crosstalk
f = 10 MHz
2.7 – 5.5
−67
dB
f = 800 MHz
2.7 – 5.5
−23
f = 1.1 GHz
2.7 – 5.5
−19
PSRR
Power Supply Ripple
Rejection
From VCC unto D+/D−,
f = 217 Hz, RL = 50 W
2.7 – 5.5
108
dB
DYNAMIC TIMING
tPD
Propagation Delay
(Notes 5 and 6)
VNOn or VNCn = 0V, RL = 50 W,
2.7 – 5.5
0.25
ns
tON
Turn−On Time
VIS = 1 V, RL = 50 W, CL = 7 pF (fix-
ture only)
2.7 – 5.5
ms
EN or SEL to AUDP/AUDN
2.2
EN or SEL to HDP/HDN
6.2
tOFF
Turn−Off Time
VIS = 1 V, RL = 50 W, CL = 7 pF (fix-
ture only)
2.7 – 5.5
ns
EN or SEL to AUDP/AUDN
67
EN or SEL to HDP/HDN
1200
tsk(b−b)
Bit to bit skew
Within the same differential channel
2.7 – 5.5
5
ps
tsk(ch−ch)
Channel to channel skew
Maximum skew between all chan-
nels
2.7 – 5.5
5
ps
5. Guaranteed by design.
6. No other delays than the RC network formed by the load resistance and the load capacitance of the switch are added on the bus. For a 10
pF load, this delay is 5 ns which is much smaller than rise and fall time of typical driving systems. Propagation delays on the bus are
determined by the driving circuit on the driving side and its interactions with the load of the driven side.


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