© Semiconductor Components Industries, LLC, 2016

September, 2016 − Rev. 4

1

Publication Order Number:

CAV25512/D

CAV25512

512-Kb SPI Serial CMOS

EEPROM

Description

The CAV25512 is a 512−Kb Serial CMOS EEPROM device

internally organized as 64Kx8 bits. This features a 128−byte page

write buffer and supports the Serial Peripheral Interface (SPI)

protocol. The device is enabled through a Chip Select (CS) input. In

addition, the required bus signals are clock input (SCK), data input

(SI) and data output (SO) lines. The HOLD input may be used to pause

any serial communication with the CAV25512 device. The device

features software and hardware write protection, including partial as

well as full array protection.

On−Chip ECC (Error Correction Code) makes the device suitable

for high reliability applications.

Features

Compliant

SI

SO

CAV25512

SCK

CS

WP

HOLD

Figure 1. Functional Symbol

This document contains information on some products that are still under development.

ON Semiconductor reserves the right to change or discontinue these products without

notice.

www.onsemi.com

SI

HOLD

WP

SO

CS

1

See detailed ordering and shipping information in the package

dimensions section on page 14 of this data sheet.

ORDERING INFORMATION

SOIC−8

V SUFFIX

CASE 751BD

SCK

SOIC (V), TSSOP (Y)

TSSOP−8

Y SUFFIX

CASE 948AL

Chip Select

CS

Serial Data Output

SO

Write Protect

WP

Ground

Serial Data Input

SI

Serial Clock

SCK

Function

Pin Name

PIN FUNCTION

Hold Transmission Input

HOLD

Power Supply

PIN CONFIGURATION

WLCSP (C8A)

(Top View)

VCC

HOLD

VSS

WP

CS

SO

SCK

SI

Reference

Pin A1

WLCSP−8

C8A SUFFIX

CASE 567MB