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CAV24C02WE-GT3 Datasheet(PDF) 3 Page - ON Semiconductor

Part # CAV24C02WE-GT3
Description  2-Kb, 4-Kb, 8-Kb and 16-Kb I2C CMOS Serial EEPROM
Download  15 Pages
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

CAV24C02WE-GT3 Datasheet(HTML) 3 Page - ON Semiconductor

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CAV24C02, CAV24C04, CAV24C08, CAV24C16
www.onsemi.com
3
Table 3. D.C. OPERATING CHARACTERISTICS
(VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified.)
Symbol
Parameter
Test Conditions
Min
Max
Units
ICCR
Read Current
Read, fSCL = 400 kHz
1
mA
ICCW
Write Current
Write, fSCL = 400 kHz
2
mA
ISB
Standby Current
All I/O Pins at GND or VCC
TA = −40°C to +125°C
5
mA
IL
I/O Pin Leakage
Pin at GND or VCC
2
mA
VIL
Input Low Voltage
−0.5
0.3 x VCC
V
VIH
Input High Voltage
A0, A1, A2 and WP
0.7 x VCC
VCC + 0.5
V
SCL and SDA
0.7 x VCC
5.5
V
VOL
Output Low Voltage
VCC > 2.5 V, IOL = 3 mA
0.4
V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
Table 4. PIN IMPEDANCE CHARACTERISTICS (VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified.)
Symbol
Parameter
Conditions
Max
Units
CIN (Note 4)
SDA Pin Capacitance
VIN = 0 V, f = 1.0 MHz, VCC = 5.0 V
8
pF
Other Pins
6
pF
IWP (Note 5)
WP Input Current
VIN < VIH, VCC = 5.5 V
130
mA
VIN < VIH, VCC = 3.6 V
120
VIN < VIH, VCC = 2.5 V
80
VIN > VIH
2
IA (Note 5)
Address Input Current
(A0, A1, A2)
VIN < VIH, VCC = 5.5 V
50
mA
VIN < VIH, VCC = 3.6 V
35
VIN < VIH, VCC = 2.5 V
25
VIN > VIH
2
4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
5. When not driven, the WP, A0, A1 and A2 pins are pulled down to GND internally. For improved noise immunity, the internal pull−down is relatively
strong; therefore the external driver must be able to supply the pull−down current when attempting to drive the input HIGH. To conserve power,
as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pull−down reverts to a weak current source.


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