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DM9102 Datasheet(PDF) 35 Page - List of Unclassifed Manufacturers |
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DM9102 Datasheet(HTML) 35 Page - List of Unclassifed Manufacturers |
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35 / 77 page  DM9102A Single Chip Fast Ethernet NIC controller Final 35 Version: DM9102A-DS-F03 August 28, 2000 3 CRDOUT 1,RW Data_Out from EEPROM This bit is set to reflect the signal status of EEDI pin when EEPROM mode is selected. 2 CRDIN 1,RW Data_In to EEPROM This bit is set to generate the output signal to EEDO pin when EEPROM mode is selected. 1 CRCLK 1,RW Clock to EEPROM This bit is set to generate the output clock to EECLK pin when EEPROM mode is selected. 0 CRCS 1,RW Chip_Select to EEPROM This bit is set to generate the output signal to EECS pin when EEPROM mode is selected. 11. Programming ROM Address Register (CR10) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 98 7 6 5 4 3 2 1 0 Bit Name Default Description 17:0 BADR Unpredictable Boot ROM Address This field contains the address pointer for Boot ROM when the mode of programming by register is selected. 12. General Purpose Timer Register (CR11) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 98 7 6 5 4 3 2 1 0 Bit Name Default Description 16 TCON 0,RW Continuous Mode of Timer When this bit is set, the timer will continuously re-initiated upon the set time is up. When reset, the timer will be one-shot response after BCLK value is programmed. 15:0 MBCLK 0000h,RW Multiple of Base Clock This field set the iteration number of base clock. The base clock duration is defined to be 81.92us --- for MII port/100M is selected 2us --- for MII port/10M is selected 13. PHY Status Register (CR12) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 98 7 6 54 3 2 1 0 Bit Name Default Description |
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