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DM9102AT Datasheet(PDF) 37 Page - List of Unclassifed Manufacturers |
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DM9102AT Datasheet(HTML) 37 Page - List of Unclassifed Manufacturers |
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37 / 77 page  DM9102A Single Chip Fast Ethernet NIC controller Final 37 Version: DM9102A-DS-F03 August 28, 2000 24:22 ERIT 000,RW Early Receive Interrupt Threshold These three bits determine the threshold of the received packet data from RX FIFO to host memory. bit24 bit 23 bit22 threshold (percentage) 0 0 0 Disable 0 0 1 12.5% 0 1 0 25.0% 0 1 1 37.5% 1 0 0 50.0% 1 0 1 62.5% 1 1 0 75.0% 1 1 1 87.5% 21:16 FIFOT 000000 ,RW RX FIFO flow control threshold option The value of bit21~16 determine the threshold of RX FIFO overflow when in flow control mode. The exact threshold is 32bytes multiplied by this value. 15 TXPM 0,RW Transmit pause packet condition control 1 = Indicate Transmit pause packet either CR15<11> or CR15<12> is set. 0 = Indicate Transmit pause packet both CR15<11> and CR15<12> are set. 14 TXP0 0,RW Transmit pause packet Set to Transmit pause packet with pause timer = 0000h 13 TXPF 0,RW Transmit pause packet Set to Transmit pause packet with pause timer = FFFFh, this bit will be cleared if packet had transmitted. 12 TXPE1 0,RW Transmit pause packet enable Set to enable Transmit pause packet if descriptor unavailable 11 TXPE2 0.RW Transmit pause packet enable Set to enable Transmit pause packet with time = FFFFh if FIFO near overflow, or with time = 0000h if FIFO empty. 10 FLCE 0,RW Flow Control Enable Set to enable the decode of the pause packet. 9 RXPS 0,R/C The latched status of the decode of the pause packet. 8 Reserved 0,RO Reserved. 7 RXPCS 0,RO Of the decode of the pause packet. 6 VLAN 0,RW VLAN Capability Enable It is set to enable the VLAN mode. 5 TWDR 0,RW Time Interval of Watchdog Release This bit is used to select the time interval between receive Watchdog timer expiration until re-enabling of the receive channel. When this bit is set, the time interval is 40~48 bits time. When this bit is reset, it is 16~24 bits time. 4 TWDE 0,RW Watchdog Timer Disable When set, the Watchdog Timer is disabled. Otherwise it is enabled. 3 Reserved 0,RO Reserved |
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