CY7C63000/CY7C63001
CY7C63100/CY7C63101
CY7C63200/CY7C63201
PRELIMINARY
7
5.0
Functional Description
The Cypress CY7C63000/1, CY7C63100/1, and CY7C63200/1 USB microcontrollers are optimized for human-interface comput-
er peripherals such as a mouse, joystick, and gamepad. Cypress USB microcontrollers conform to the low-speed (1.5 Mbps)
requirements of the USB Specification version 1.0. Each micorcontroller is a self-contained unit with a USB interface engine, USB
transceivers, an 8-bit RISC microcontroller, a clock oscillator, timers, and program memories. It supports one USB device address
and two end points.
The 6 MHz clock generated by the on-chip oscillator is stepped up to 12 MHz to drive the microcontroller. A RISC architecture
with 35 instructions is chosen to provide the best balance between performance and product cost.
5.1
Memory Organization
The memory in the USB Controller is organized into user program memory in EPROM space and data memory in SRAM space.
5.1.1
Program Memory Organization
The 14-bit Program Counter (PC) is capable of addressing 16K bytes of program space. However, the program space of the
CY7C63000, CY7C63100 and CY7C63200 is 2K bytes. For applications requiring more program space, the CY7C63001,
CY7C63101 and CY7C63201 each offer 4K bytes of EPROM. The program memory space is divided into two functional groups:
Interrupt Vectors and program code.
The interrupt vectors occupy the first 16 bytes of the program space. Each vector is 2 bytes long. After a reset, the Program
Counter points to location zero of the program space.
Figure 5-1 shows the organization of the Program memory Space.
5.1.2
Security Fuse Bit
The Cypress USB microcontroller includes a security fuse bit. When the security fuse is programmed, the EPROM program
memory outputs 0xFF to the EPROM programmer, thus protecting the user’s code.
4.0
Pin Description
Name
Description
VDD
1 pin. Connects to the USB power source or to a nominal 5V power supply. Actual VCC range can vary
between 4.0V and 5.25V
VSS
1 pin. Connects to ground
VPP
1 pin. Used in programming the on-chip EPROM. This pin should be tied to ground during normal
operations.
XTALIN
1 pin. Input from an external ceramic resonator, crystal, or clock
XTALOUT
1 pin. Return path for the ceramic resonator or crystal
P0.0–P0.7,
P1.0–P1.7
16 pins. P0.0–P0.7 are the 8 I/O lines in Port 0. P1.0–P1.7 are the 8 I/O lines in Port 1. Please note
that P1.0–P1.1 are supported in the CY7C6320x and P1.0–P1.3 are supported in the CY7C6300x. All
I/O pins are pulled up internally by 16K
Ω resistors. However, the sink current of each pin can be
programmed to one of sixteen levels. Besides functioning as general purpose I/O lines, each pin can
be programmed as an interrupt input. The interrupt is edge-triggered, with programmable polarity.
D+, D–
2 pins. Open-drain I/O with 2 pins. Bidirectional USB data lines. An external 7.5 K
Ω resistor must be
connected between the D– pin and VCC to select low-speed USB operation.
CEXT
1 pin. Open-drain output with Schmitt trigger input. The input is connected to a level-sensitive (HIGH)
interrupt. CEXT may be connected to an external RC to generate a wake-up from Suspend mode. See
Section 5.6.