CY7C1352F
Document #: 38-05211 Rev. *C
Page 9 of 13
AC Test Loads and Waveforms
Notes:
9. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC)> -2V (Pulse width less than tCYC/2).
10. TPower-up: Assumes a linear ramp from 0V to VDD (min.) within 200ms. During this time VIH < VDD and VDDQ < VDD.
11. Tested initially and after any design or process changes that may affect these parameters.
1ns
OUTPUT
R = 317
Ω
R = 351
Ω
5pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
OUTPUT
RL = 50Ω
Z0 = 50Ω
VL = 1.5V
3.3V
ALL INPUT PULSES
VDD
GND
90%
10%
90%
10%
≤ 1ns
≤ 1ns
(c)
OUTPUT
R = 1667
Ω
R =1538
Ω
5pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
OUTPUT
RL = 50Ω
Z0 = 50Ω
VL = 1.25V
2.5V
ALL INPUT PULSES
VDD
GND
90%
10%
90%
10%
≤ 1ns
≤ 1ns
(c)
3.3V I/O Test Load
2.5V I/O Test Load
Switching Characteristics Over the Operating Range[12, 13, 14, 15, 16, 17]
Parameter
Description
250 MHz
225 MHz
200 MHz
166 MHz
133 MHz
100 MHz
Unit
Min. Max Min. Max Min. Max Min. Max Min. Max Min. Max
tPOWER
VDD (typical) to the first Access[12]
1
1
1
1
11
ms
Clock
tCYC
Clock Cycle Time
4.0
4.4
5.0
6.0
7.5
10
ns
tCH
Clock HIGH
1.7
2.0
2.0
2.5
3.0
3.5
ns
tCL
Clock LOW
1.7
2.0
2.0
2.5
3.0
3.5
ns
Output Times
tCO
Data Output Valid After CLK Rise
2.6
2.6
2.8
3.5
4.0
4.5
ns
tDOH
Data Output Hold After CLK Rise
1.0
1.0
1.0
2.0
2.0
2.0
ns
tCLZ
Clock to Low-Z[13, 14, 15]
0
0
0
0
00
ns
tCHZ
Clock to High-Z[13, 14, 15]
2.6
2.6
2.8
3.5
4.0
4.5
ns
tOEV
OE LOW to Output Valid
2.6
2.6
2.8
3.5
4.0
4.5
ns
tOELZ
OE LOW to Output Low-Z[13, 14, 15]
0
0
0
0
00
ns
tOEHZ
OE HIGH to Output High-Z[13, 14, 15]
2.6
2.6
2.8
3.5
4.0
4.5
ns
Set-up Times
tAS
Address Set-up Before CLK Rise
0.8
1.2
1.2
1.5
1.5
1.5
ns
Shaded areas contain advance information.
Notes:
12. This part has a voltage regulator internally; tpower is the time that the power needs to be supplied above VDD minimum initially before a read or write operation
can be initiated.
13. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
14. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve Three-state prior to Low-Z under the same system conditions.
15. This parameter is sampled and not 100% tested.
16. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V.
17. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
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