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CY7C1352F-200AI Datasheet(PDF) 11 Page - Cypress Semiconductor

Part # CY7C1352F-200AI
Description  4-Mbit (256Kx18) Pipelined SRAM with NoBL??Architecture
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1352F-200AI Datasheet(HTML) 11 Page - Cypress Semiconductor

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CY7C1352F
Document #: 38-05211 Rev. *C
Page 11 of 13
NOP, STALL, and DESELECT Cycles[18, 19, 21]
ZZ Mode Timing[22, 23]
Notes:
21. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle.
22. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.
23. DQs are in high-Z when exiting ZZ sleep mode.
Switching Waveforms (continued)
READ
Q(A3)
456
789
10
CLK
CE
WE
CEN
BW[A:B]
ADV/LD
ADDRESS
A3
A4
A5
D(A4)
Data
In-Out (DQ)
A1
Q(A5)
WRITE
D(A4)
STALL
WRITE
D(A1)
123
READ
Q(A2)
STALL
NOP
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
DON’T CARE
UNDEFINED
tCHZ
A2
D(A1)
Q(A2)
Q(A3)
t
ZZ
I
SUPPLY
CLK
ZZ
t
ZZREC
ALL INPUTS
(except ZZ)
I
DDZZ
t
ZZI
t
RZZI
DESELECT or READ Only


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