CY22392
Document #: 38-07013 Rev. *D
Page 5 of 8
Electrical Characteristics
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
IOH
Output High Current[3]
VOH =VDD – 0.5, VDD =3.3 V
12
24
–
mA
IOL
Output Low Current[3]
VOL =0.5V, VDD =3.3 V
12
24
–
mA
CXTAL_MIN
Crystal Load Capacitance[3]
Capload at minimum setting
–
6
–
pF
CXTAL_MAX
Crystal Load Capacitance[3]
Capload at maximum setting
–
30
–
pF
CLOAD_IN
Input Pin Capacitance[3]
Except crystal pins
–
7
–
pF
VIH
HIGH-Level Input Voltage
CMOS levels,% of AVDD
70%
–
–
AVDD
VIL
LOW-Level Input Voltage
CMOS levels,% of AVDD
–
–
30%
AVDD
IIH
Input HIGH Current
VIN =AVDD –0.3 V
–
<1
10
µA
IIL
Input LOW Current
VIN =+0.3V
–
<1
10
µA
IOZ
Output Leakage Current
Three-state outputs
–
10
µA
IDD
Total Power Supply Current
3.3V Power Supply; 2 outputs @
166 MHz; 4 outputs @ 83 MHz
–
100
–
mA
3.3V Power Supply; 2 outputs @
20 MHz; 4 outputs @ 40 MHz
–
50
–
mA
IDDS
Total Power Supply Current in
Shutdown Mode
Shutdown active
–
5
20
µA
Switching Characteristics
Parameter
Name
Description
Min.
Typ.
Max.
Unit
1/t1
Output Frequency[3, 4]
Clock output limit, Commercial
–
–
200
MHz
Clock output limit, Industrial
–
–
166
MHz
t2
Output Duty Cycle[3, 5]
Duty cycle for outputs, defined as t2 ÷ t1,
Fout < 100 MHz, divider >= 2, measured at VDD/2
45%
50%
55%
Duty cycle for outputs, defined as t2 ÷ t1,
Fout > 100 MHz or divider = 1, measured at VDD/2
40%
50%
60%
t3
Rising Edge Slew Rate[3] Output clock rise time, 20% to 80% of VDD
0.75
1.4
–
V/ns
t4
Falling Edge Slew
Rate[3]
Output clock fall time, 20% to 80% of VDD
0.75
1.4
–
V/ns
t5
Output three-state
Timing[3]
Time for output to enter or leave three-state mode
after SHUTDOWN/OE switches
–
150
300
ns
t6
Clock Jitter[3, 6]
Peak-to-peak period jitter, CLK outputs measured
at VDD/2
–400
–
ps
t7
Lock Time[3]
PLL Lock Time from Power-up
–
1.0
3
ms
Notes:
3. Guaranteed by design, not 100% tested.
4. Guaranteed to meet 20%–80% output thresholds and duty cycle specifications.
5. Reference Output duty cycle depends on XTALIN duty cycle.
6. Jitter varies significantly with configuration. Reference Output jitter depends on XTALIN jitter and edge rate.