Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF HTML

MAX3872 Datasheet(PDF) 4 Page - Maxim Integrated Products

Part No. MAX3872
Description  Multirate Clock and Data Recovery with Limiting Amplifier
Download  13 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  MAXIM [Maxim Integrated Products]
Homepage  http://www.maxim-ic.com
Logo 

MAX3872 Datasheet(HTML) 4 Page - Maxim Integrated Products

 
Zoom Inzoom in Zoom Outzoom out
 4 / 13 page
background image
Multirate Clock and Data Recovery
with Limiting Amplifier
4
_______________________________________________________________________________________
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, TA = -40°C to +85°C. Typical values are at VCC = +3.3V and TA = +25°C, unless otherwise noted.) (Note 5)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CML OUTPUT SPECIFICATIONS (SDO
±, SCLKO±)
Output Edge Speed
tr, tf
20% to 80%
110
ps
CML Output Differential Swing
RC = 100
Ω differential
600
800
1000
mVP-P
Clock-to-Q Delay
tCLK-Q
(Note 9)
-50
+50
ps
PLL ACQUISITION/LOCK SPECIFICATIONS
Tolerated Consecutive Identical
Digits
BER
≤ 10-10
2000
bits
Acquisition Time
Figure 4 (Note 10)
5.5
ms
LOL Assert Time
Figure 4
2.3
100.0
µs
Low-Frequency Cutoff for
DC-Offset Cancellation
CAZ = 0.1µF
4
kHz
CLOCK HOLDOVER SPECIFICATIONS
Reference Clock Frequency
Table 3
Maximum VCO Frequency Drift
(Note 11)
400
ppm
Note 5:
AC characteristics are guaranteed by design and characterization.
Note 6:
Jitter tolerance is guaranteed (BER
≤ 10-10) within this input voltage range. Input threshold adjust is disabled with VCTRL
connected to VCC.
Note 7:
Measured at OC-48 data rate using a 100mVP-P differential swing with a 20mVDC offset and an edge speed of 145ps (4th-
order Bessel filter with f3dB = 1.8GHz).
Note 8:
Measured with 10mVP-P differential input, 223 - 1 PRBS pattern at OC-48 with bandwidth from 12kHz to 20MHz.
Note 9:
Relative to the falling edge of the SCLKO+ (Figure 3).
Note 10: Measured using a 0.82µF loop-filter capacitor initialized to +3.6V.
Note 11: Measured at OC-48 data rate under LOL condition with the CDR clock output set by the external reference clock.
(a) AC-COUPLED SINGLE-ENDED INPUT
(b) DC-COUPLED SINGLE-ENDED INPUT
5mV
5mV
800mV
800mV
VCC + 0.4V
VCC
VCC - 0.4V
VCC
VCC - 0.4V
VCC - 0.8V
Figure 1. Definition of Input Voltage Swing
1.3
2.10
THRESHOLD-
SETTING
ACCURACY
(PART-TO-PART
VARIATION OVER
PROCESS)
VCTRL (V)
VTH (mV)
+188
+170
+152
-152
-170
-188
THRESHOLD-SETTING STABILITY
(OVERTEMPERATURE AND POWER SUPPLY)
0.3
1.1
Figure 2. Relationship Between Control Voltage and Threshold
Voltage
Timing Diagrams


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13 


Datasheet Download




Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn