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NLAST4051DTR2G Datasheet(PDF) 1 Page - ON Semiconductor |
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NLAST4051DTR2G Datasheet(HTML) 1 Page - ON Semiconductor |
1 / 12 page © Semiconductor Components Industries, LLC, 2015 November, 2015 − Rev. 5 1 Publication Order Number: NLAST4051/D NLAST4051 Analog Multiplexer/ Demultiplexer TTL Compatible, Single−Pole, 8−Position Plus Common Off The NLAST4051 is an improved version of the MC14051 and MC74HC4051 fabricated in sub−micron Silicon Gate CMOS technology for lower RDS(on) resistance and improved linearity with low current. This device may be operated either with a single supply or dual supply up to ±3 V to pass a 6 VPP signal without coupling capacitors. When operating in single supply mode, it is only necessary to tie VEE, pin 7 to ground. For dual supply operation, VEE is tied to a negative voltage, not to exceed maximum ratings. Translation is provided in the device, the Address and Inhibit are standard TTL level compatible. For CMOS compatibility see NLAS4051. Pin for pin compatible with all industry standard versions of ‘4051.’ Features • Improved RDS(on) Specifications • Pin for Pin Replacement for MAX4051 and MAX4051A − One Half the Resistance Operating at 5.0 V • Single or Dual Supply Operation − Single 3.0 − 5.0 V Operation, or Dual ±3 V Operation − With VCC of 3.0 to 3.3 V, Device Can Interface with 1.8 V Logic, − No Translators Needed − Address and Inhibit Logic are Over−Voltage Tolerant and May Be − Driven Up +6 V Regardless of VCC • Address and Inhibit Pins Standard TTL Compatible − Greatly Improved Noise Margin Over MAX4051 and MAX4051A − True TTL Compatibility VIL = 0.8 V, VIH = 2.0 V • Improved Linearity Over Standard HC4051 Devices • Space Saving TSSOP Package • NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable • These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant Figure 1. Pin Connection (Top View) 15 16 14 13 12 11 10 2 1 345 67 VCC 9 8 NO2 NO4 NO0 NO6 ADDC ADDB ADDA NO1 NO3 COM NO7 NO5 Inhibit VEE GND www.onsemi.com MARKING DIAGRAM TSSOP−16 DT SUFFIX CASE 948F See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. ORDERING INFORMATION A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package AST 4051 ALYW G G (Note: Microdot may be in either location) 1 1 16 |
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