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S25FS064S Datasheet(PDF) 4 Page - Cypress Semiconductor |
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S25FS064S Datasheet(HTML) 4 Page - Cypress Semiconductor |
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4 / 147 page  Document Number: 002-03631 Rev. *C Page 4 of 147 S25FS064S PRELIMINARY 1. Overview 1.1 General Description The Cypress FS-S Family of devices are Flash non-volatile memory products using: MirrorBit technology - that stores two data bits in each memory array transistor Eclipse architecture - that dramatically improves program and erase performance 65 nm process lithography The FS-S Family connects to a host system via a Serial Peripheral Interface (SPI). Traditional SPI single bit serial input and output (Single I/O or SIO) is supported as well as optional two bit (Dual I/O or DIO) and four bit wide Quad I/O (QIO) and Quad Peripheral Interface (QPI) commands. In addition, there are Double Data Rate (DDR) read commands for QIO and QPI that transfer address and read data on both edges of the clock. The FS-S Eclipse architecture features a Page Programming Buffer that allows up to 512 bytes to be programmed in one operation, resulting in faster effective programming and erase than prior generation SPI program or erase algorithms. Executing code directly from Flash memory is often called Execute-In-Place or XIP. By using FS-S Family devices at the higher clock rates supported, with Quad or DDR-Quad commands, the instruction read transfer rate can match or exceed traditional parallel interface, asynchronous, NOR Flash memories, while reducing signal count dramatically. The FS-S Family products offer high densities coupled with the flexibility and fast performance required by a variety of mobile or embedded applications. They are an excellent solution for systems with limited space, signal connections, and power. They are ideal for code shadowing to RAM, executing code directly (XIP), and storing reprogrammable data. 1.2 Migration Notes 1.2.1 Features Comparison The FS-S Family is command subset and footprint compatible with prior generation FL-S, and FL-P families. However, the power supply and interface voltages are nominal 1.8V. Table 1.1 Cypress SPI Families Comparison Parameter FS-S FS-S FL-S FL-P Technology Node 65nm 65nm 65nm 90nm Architecture MirrorBit® Eclipse™ MirrorBit® Eclipse™ MirrorBit® Eclipse™ MirrorBit® Release Date In Production 2H2015 In Production In Production Density 128Mb, 256Mb 512MB 64Mb 128Mb 256Mb 512Mb 32Mb - 256Mb Bus Width x1, x2, x4 x1, x2, x4 x1, x2, x4 x1, x2, x4 Supply Voltage 1.7V - 2.0V 1.7V - 2.0V 2.7V - 3.6V / 1.65V - 3.6V VIO 2.7V - 3.6V Normal Read Speed (SDR) 6MB/s (50MHz) 6MB/s (50MHz) 6MB/s (50MHz) 5MB/s (40MHz) Fast Read Speed (SDR) 16.5MB/s (133MHz) 16.5MB/s (133MHz) 16.5MB/s (133MHz) 13MB/s (104MHz) Dual Read Speed (SDR) 33MB/s (133MHz) 33MB/s (133MHz) 26MB/s (104MHz) 20MB/s (80MHz) Quad Read Speed (SDR) 66MB/s (133MHz) 66MB/s (133MHz) 52MB/s (104MHz) 40MB/s (80MHz) Quad Read Speed (DDR) 80MB/s (80 MHz) 80Mb/s(80Mhz ) 66MB/s (66MHz) - Program Buffer Size 256B / 512B 256B / 512B 256B / 512B 256B Erase Sector Size 64KB / 256KB 64KB / 256KB 64KB / 256KB 64KB / 256KB Parameter Sector Size 4KB (option) 4KB (option) 4KB (option) 4KB Sector Erase Rate (typ.) 500 KB/s 500 KB/s 500 KB/s 130 KB/s Page Programming Rate (typ.) 1.0 MB/s (256B) 1.2 MB/s (512B) 1.0 MB/s (256B) 1.2 MB/s (512B) 1.2 MB/s (256B) 1.5 MB/s (512B) 170 KB/s OTP 1024B 1024B 1024B 506B Advanced Sector Protection Yes Yes Yes No |
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