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CY8C4247AZI-L433 Datasheet(PDF) 8 Page - Cypress Semiconductor |
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CY8C4247AZI-L433 Datasheet(HTML) 8 Page - Cypress Semiconductor |
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8 / 46 page  PSoC® 4: PSoC 4200-L Family Datasheet Document Number: 001-91686 Rev. *E Page 8 of 46 UDBs can be clocked from a clock divider block, from a port interface (required for peripherals such as SPI), and from the DSI network directly or after synchronization. A port interface is defined, which acts as a register that can be clocked with the same source as the PLDs inside the UDB array. This allows faster operation because the inputs and outputs can be registered at the port interface close to the I/O pins and at the edge of the array. The port interface registers can be clocked by one of the I/Os from the same port. This allows interfaces such as SPI to operate at higher clock speeds by eliminating the delay for the port input to be routed over DSI and used to register other inputs. The port interface is shown in Figure 7. The UDBs can generate interrupts (one UDB at a time) to the interrupt controller. The UDBs retain the ability to connect to any pin on the chip through the DSI. Figure 7. Port Interface Fixed Function Digital Timer/Counter/PWM (TCPWM) Block The TCPWM block consists of four 16-bit counters with user-programmable period length. There is a Capture register to record the count value at the time of an event (which may be an I/O event), a period register which is used to either stop or auto-reload the counter when its count is equal to the period register, and compare registers to generate compare value signals, which are used as PWM duty cycle outputs. The block also provides true and complementary outputs with program- mable offset between them to allow use as deadband program- mable complementary PWM outputs. It also has a Kill input to force outputs to a predetermined state; for example, this is used in motor drive systems when an overcurrent state is indicated and the PWMs driving the FETs need to be shut off immediately with no time for software intervention. The PSoC 4200-L has eight TCPWM blocks. Serial Communication Blocks (SCB) The PSoC 4200-L has four SCBs, which can each implement an I2C, UART, or SPI interface. I2C Mode: The hardware I2C block implements a full multi-master and slave interface (it is capable of multimaster arbitration). This block is capable of operating at speeds of up to 1 Mbps (Fast Mode Plus) and has flexible buffering options to reduce interrupt overhead and latency for the CPU. It also supports EzI2C that creates a mailbox address range in the memory of the PSoC 4200-L and effectively reduces I2C commu- nication to reading from and writing to an array in memory. In addition, the block supports an 8-deep FIFO for receive and transmit which, by increasing the time given for the CPU to read data, greatly reduces the need for clock stretching caused by the CPU not having read data on time. The FIFO mode is available in all channels and is very useful in the absence of DMA. The I2C peripheral is compatible with the I2C Standard-mode, Fast-mode, and Fast-mode Plus devices as defined in the NXP I2C-bus specification and user manual (UM10204). The I2C bus I/O is implemented with GPIO in open-drain modes. UART Mode: This is a full-feature UART operating at up to 1 Mbps. It supports automotive single-wire interface (LIN), infrared interface (IrDA), and SmartCard (ISO7816) protocols, all of which are minor variants of the basic UART protocol. In addition, it supports the 9-bit multiprocessor mode that allows addressing of peripherals connected over common RX and TX lines. Common UART functions such as parity error, break detect, and frame error are supported. An 8-deep FIFO allows much greater CPU service latencies to be tolerated. SPI Mode: The SPI mode supports full Motorola SPI, TI SSP (essentially adds a start pulse used to synchronize SPI Codecs), and National Microwire (half-duplex form of SPI). The SPI block can use the FIFO. USB Device A Full-speed USB 2.0 device interface is provided. It has a Control endpoint and eight other endpoints. The interface has a USB transceiver and can be operated from the IMO obviating the need for a crystal oscillator. Clock Selector Block from UDB 9 Digital GlobalClocks 3 DSI Signals , 1 I/O Signal 4 Reset Selector Block from UDB 2 2 Input Registers Output Registers To DSI 8 From DSI 8 8 8 Enables 8 From DSI 4 4 7 6 . . . 0 7 6 . . . 0 3 2 1 0 High Speed I/O Matrix To Clock Tree [0] [0] [1] [1] [1] [1] |
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