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CY8C4246AZI-L445 Datasheet(PDF) 5 Page - Cypress Semiconductor |
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CY8C4246AZI-L445 Datasheet(HTML) 5 Page - Cypress Semiconductor |
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5 / 46 page  PSoC® 4: PSoC 4200-L Family Datasheet Document Number: 001-91686 Rev. *E Page 5 of 46 Functional Definition CPU and Memory Subsystem CPU The Cortex-M0 CPU in the PSoC 4200-L is part of the 32-bit MCU subsystem, which is optimized for low-power operation with extensive clock gating. Most instructions are 16 bits in length and execute a subset of the Thumb-2 instruction set. This enables fully compatible binary upward migration of the code to higher performance processors such as the Cortex-M3 and M4, thus enabling upward compatibility. The Cypress implementation includes a hardware multiplier that provides a 32-bit result in one cycle. It includes a nested vectored interrupt controller (NVIC) block with 32 interrupt inputs and also includes a Wakeup Interrupt Controller (WIC), which can wake the processor up from the Deep Sleep mode allowing power to be switched off to the main processor when the chip is in the Deep Sleep mode. The Cortex-M0 CPU provides a Non-Maskable Interrupt (NMI) input, which is made available to the user when it is not in use for system functions requested by the user. The CPU also includes a debug interface, the serial wire debug (SWD) interface, which is a 2-wire form of JTAG; the debug configuration used for PSoC 4200-L has four break-point (address) comparators and two watchpoint (data) comparators. Flash The PSoC 4200-L has a flash module with a flash accelerator, tightly coupled to the CPU to improve average access times from the flash block. The flash block is designed to deliver 2 wait-state (WS) access time at 48 MHz and with 1-WS access time at 24 MHz. The flash accelerator delivers 85% of single-cycle SRAM access performance on average. Part of the flash module can be used to emulate EEPROM operation if required. SRAM SRAM memory is retained during Hibernate. SROM A supervisory ROM that contains boot and configuration routines is provided. DMA A DMA engine is provided that can do 32-bit transfers and has chainable ping-pong descriptors. System Resources Power System The power system is described in detail in the section Power on page 15. It provides assurance that voltage levels are as required for each respective mode and either delay mode entry (on power-on reset (POR), for example) until voltage levels are as required for proper function or generate resets (brown-out detect (BOD)) or interrupts (low voltage detect (LVD)). The PSoC 4200-L operates with a single external supply over the range of 1.71 to 5.5 V and has five different power modes, transi- tions between which are managed by the power system. The PSoC 4200-L provides Sleep, Deep Sleep, Hibernate, and Stop low-power modes. Clock System The PSoC 4200-L clock system is responsible for providing clocks to all subsystems that require clocks and for switching between different clock sources without glitching. In addition, the clock system ensures that no meta-stable conditions occur. The clock system for the PSoC 4200-L consists of a crystal oscil- lator (4 to 33 MHz), a watch crystal oscillator (32 kHz), a phase-locked loop (PLL), the IMO and the ILO internal oscil- lators, and provision for an external clock. Figure 3. PSoC 4200-L MCU Clocking Architecture The clk_hf signal can be divided down to generate synchronous clocks for the UDBs, and the analog and digital peripherals. There are a total of 16 clock dividers for the PSoC 4200-L, each with 16-bit divide capability; this allows 12 to be used for the fixed-function blocks and four for the UDBs. The analog clock leads the digital clocks to allow analog events to occur before digital clock-related noise is generated. The 16-bit capability allows a lot of flexibility in generating fine-grained frequency values and is fully supported in PSoC Creator. IMO Clock Source The IMO is the primary source of internal clocking in the PSoC 4200-L. It is trimmed during testing to achieve the specified accuracy. Trim values are stored in nonvolatile latches (NVL). Additional trim settings from flash can be used to compensate for changes. The IMO default frequency is 24 MHz and it can be adjusted between 3 to 48 MHz in steps of 1 MHz. IMO tolerance with Cypress-provided calibration settings is ±2%. ILO Clock Source The ILO is a very low power oscillator, nominally 32 kHz, which is primarily used to generate clocks for peripheral operation in Deep Sleep mode. ILO-driven counters can be calibrated to the IMO to improve accuracy. Cypress provides a software component, which does the calibration. Crystal Oscillators and PLL The PSoC 4200-L clock subsystem also implements two oscil- lators: high-frequency (4 to 33 MHz) and low-frequency (32-kHz watch crystal) that can be used for precision timing applications. The PLL can generate a 48-MHz output from the high-frequency oscillator. ECO IMO WCO ILO PLL #0 clk_ext clk_hf clk_lf (optional ) dsi_in[3] dsi_out[3:0] PLL #1 dsi_in[2] dsi_in[0] dsi_in[1] |
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