SN74V215, SN74V225, SN74V235, SN74V245

512

× 18, 1024 × 18, 2048 × 18, 4096 × 18

DSP-SYNC

 FIRST-IN, FIRST-OUT MEMORIES

SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002

12

POST OFFICE BOX 655303

functional description (continued)

Table 5. Truth Table for Configuration at Reset

FL

RXI

WXI

EF/OR

FF/IR

PAE, PAF

FIFO TIMING MODE

0

0

0

Single register-buffered

empty flag

Single register-buffered

full flag

Asynchronous

Standard

0

0

1

Triple register-buffered

output-ready flag

Double register-buffered

input ready flag

Asynchronous

FWFT

0

1

0

Double register-buffered

empty flag

Double register-buffered

full flag

Asynchronous

Standard

0†

1

1

Single register-buffered

empty flag

Single register-buffered

full flag

Asynchronous

Standard

1

0

0

Single register-buffered

empty flag

Single register-buffered

full flag

Synchronous

Standard

1

0

1

Triple register-buffered

output-ready flag

Double register-buffered

input ready flag

Synchronous

FWFT

1

1

0

Double register-buffered

empty flag

Double register-buffered

full flag

Synchronous

Standard

1‡

1

1

Single register-buffered

empty flag

Single register-buffered

full flag

Asynchronous

Standard

† In daisy-chain depth expansion, FL is held low for the first-load device. The RXI and WXI inputs are driven by the

corresponding RXO and WXO outputs of the preceding device.

‡ In daisy-chain depth expansion, FL is held high for members of the expansion other than the first-load device. The RXI and

WXI inputs are driven by the corresponding RXO and WXO outputs of the preceding device.

REGISTER-BUFFERED FLAG OUTPUT SELECTION

The SN74V215, SN74V225, SN74V235, and SN74V245 can be configured during the configuration-at-reset

cycle (see Table 7) with single, double, or triple register-buffered flag output signals. The various combinations

available are described in Table 6 and Table 7. In general, going from single to double or triple register-buffered

flag outputs removes the possibility of metastable flag indications on boundary states (empty or full conditions).

The tradeoff is the addition of clock-cycle delays for the respective flag to be asserted. Not all combinations of

register-buffered flag outputs are supported. Register-buffered outputs apply to the empty flag and full flag only.

Partial flags are not affected. Table 6 and Table 7 summarize the options available.

Table 6. Register-Buffered Flag Output Options, FWFT Mode

OUTPUT READY

(OR)

INPUT READY

(IR)

PARTIAL

FLAGS

PROGRAMMING

AT RESET

FLAG TIMING

DIAGRAMS

(OR)

(IR)

FLAGS

FL

RXI

WXI

DIAGRAMS

Triple

Double

Asynchronous

0

0

1

Figure 23

Triple

Double

Synchronous

1

0

1

Figure 16, Figure 17

Table 7. Register-Buffered Flag Output Options, Standard Mode

EMPTY FLAG

(EF)

FULL FLAG

(FF)

PARTIAL

FLAGS

PROGRAMMING AT

RESET

FLAG TIMING

DIAGRAMS

(EF)

BUFFERED OUTPUT

(FF)

BUFFERED OUTPUT

FLAGS

TIMING MODE

FL

RXI

WXI

DIAGRAMS

Single

Single

Asynchronous

0

0

0

Figure 5, Figure 6

Single

Single

Synchronous

1

0

0

Figure 5, Figure 6

Double

Double

Asynchronous

0

1

0

Figure 20, Figure 22

Double

Double

Synchronous

1

1

0

Figure 20, Figure 22