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SI3024-KT Datasheet(PDF) 22 Page - List of Unclassifed Manufacturers |
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SI3024-KT Datasheet(HTML) 22 Page - List of Unclassifed Manufacturers |
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22 / 54 page  Si 30 35 22 Rev. 1.2 Figure 22. Secondary Communication Data Format—Write Cycle Figure 23. Clock Generation Subsystem The architecture of the dual PLL scheme allows for fast lock time on initial start-up, fast lock time when changing modem sample rates, high noise immunity, and the ability to change modem sample rates with a single register write. A large number of MCLK frequencies between 1 MHz and 60 MHz are supported. MCLK should be from a clean source, preferably directly from a crystal with a constant frequency and no dropped pulses. In serial mode 2, the Si3021 operates as a slave device. The clock generator is configured (by default) to set the SCLK output equal to the MCLK input. The net effect is the clock generator multiplies the MCLK input by 20. For further details of slave mode operation, refer to "Multiple Device Support" on page 25. Programming the Clock Generator As noted in Figure 23, the clock generator must output a clock equal to 1024 " Fs, where Fs is the desired sample rate. The 1024 " Fs clock is determined through programming of the following registers: Register 7—N1 divider, 8 bits. Register 8—M1 divider, 8 bits. Register 9—N2/M2 dividers, 4 bits/4 bits. Register 10—CGM, 1 bit. When using the Si3035 for modem applications, the clock generator can be programmed to allow for a single register write to change the modem sampling rate. These standard sample rates are shown in Table 17. The programming method is described below. R/W FSYNC (m ode 1) SDI D 15 D 14 D 13 D 12 D 11 D 10 D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 0 0 0 A A A A A SDO D D D D D D D D FSYNC (m ode 0) 0 1 0 1 CGM Bit MCLK 1024·Fs FUP1 FUP2 FPLL1 FPLL2 PLL1 PLL2 DIV N1 8 bits DIV 25 DIV M1 8 bits DIV N2 4 bits DIV M2 4 bits DIV 16 DIV 5 |
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