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CAT5409YI-10-T2 Datasheet(PDF) 5 Page - ON Semiconductor

Part # CAT5409YI-10-T2
Description  Quad Digital Potentiometer (POT)
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

CAT5409YI-10-T2 Datasheet(HTML) 5 Page - ON Semiconductor

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Table 5. D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Symbol
Parameter
Test Conditions
Min
Max
Units
ICC
Power Supply Current
fSCL = 400 kHz
1
mA
ISB
Standby Current (VCC = 5 V)
VIN = GND or VCC, SDA Open
1
mA
ILI
Input Leakage Current
VIN = GND to VCC
10
mA
ILO
Output Leakage Current
VOUT = GND to VCC
10
mA
VIL
Input Low Voltage
−1
VCC x 0.3
V
VIH
Input High Voltage
VCC x 0.7
VCC + 1.0
V
VOL1
Output Low Voltage (VCC = 3 V)
IOL = 3 mA
0.4
V
Table 6. CAPACITANCE (Note 8) (TA = 25C, f = 1.0 MHz, VCC = 5 V)
Symbol
Test
Conditions
Max
Units
CI/O
Input/Output Capacitance (SDA)
VI/O = 0 V
8
pF
CIN
Input Capacitance (A0, A1, A2, A3, SCL, WP)
VIN = 0 V
6
pF
8. This parameter is tested initially and after a design or process change that affects the parameter.
Table 7. A.C. CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Symbol
Parameter
Min
Typ
Max
Units
fSCL
Clock Frequency
400
kHz
TI (Note 10)
Noise Suppression Time Constant at SCL, SDA Inputs
50
ns
tAA
SLC Low to SDA Data Out and ACK Out
0.9
ms
tBUF (Note 10)
Time the bus must be free before a new transmission can start
1.2
ms
tHD:STA
Start Condition Hold Time
0.6
ms
tLOW
Clock Low Period
1.2
ms
tHIGH
Clock High Period
0.6
ms
tSU:STA
Start Condition SetupTime (for a Repeated Start Condition)
0.6
ms
tHD:DAT
Data in Hold Time
0
ns
tSU:DAT
Data in Setup Time
100
ns
tR (Note 10)
SDA and SCL Rise Time
0.3
ms
tF (Note 10)
SDA and SCL Fall Time
300
ns
tSU:STO
Stop Condition Setup Time
0.6
ms
tDH
Data Out Hold Time
50
ns
Table 8. POWER UP TIMING (Note 10)
Symbol
Parameter
Max
Units
tPUR
Power-up to Read Operation
1
ms
tPUW
Power-up to Write Operation
1
ms
Table 9. WRITE CYCLE LIMITS (Note 9)
Symbol
Parameter
Max
Units
tWR
Write Cycle Time
5
ms
9. The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write
cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.


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