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CS8415A-IZ Datasheet(PDF) 8 Page - Cirrus Logic |
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CS8415A-IZ Datasheet(HTML) 8 Page - Cirrus Logic |
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8 / 42 page  CS8415A 8 SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE (Inputs: Logic 0 = 0 V, Logic 1 = VL+; CL = 20 pF) Notes: 12. If Fs is lower than 46.875 kHz, the maximum CCLK frequency should be less than 128 Fs. This is dictated by the timing requirements necessary to access the Channel Status and User Bit buffer memory. Access to the control register file can be carried out at the full 6 MHz rate. The minimum allowable input sample rate is 8 kHz, so choosing CCLK to be less than or equal to 1.024 MHz should be safe for all possible conditions. 13. Data must be held for sufficient time to bridge the transition time of CCLK. 14. For fsck <1 MHz. Parameter Symbol Min Typ Max Units CCLK Clock Frequency (Note 12) fsck 0- 6.0 MHz CS High Time Between Transmissions tcsh 1.0 - - µs CS Falling to CCLK Edge tcss 20 - - ns CCLK Low Time tscl 66 - - ns CCLK High Time tsch 66 - - ns CDIN to CCLK Rising Setup Time tdsu 40 - - ns CCLK Rising to DATA Hold Time (Note 13) tdh 15 - - ns CCLK Falling to CDOUT Stable tpd - - 50 ns Rise Time of CDOUT tr1 - - 25 ns Fall Time of CDOUT tf1 - - 25 ns Rise Time of CCLK and CDIN (Note 14) tr2 - - 100 ns Fall Time of CCLK and CDIN (Note 14) tf2 - - 100 ns t r2 t f2 t dsu t dh t sch t scl CS CCLK CDIN t css t pd CDOUT t csh Figure 3. SPI Mode Timing |
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Similar Description - CS8415A-IZ |
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