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XMC4700-F144x1536 Datasheet(PDF) 85 Page - Infineon Technologies AG |
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XMC4700-F144x1536 Datasheet(HTML) 85 Page - Infineon Technologies AG |
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85 / 130 page  XMC4700 / XMC4800 XMC4000 Family Electrical Parameters Preliminary Data Sheet 85 V0.7, 2015-10 3.3.9 Peripheral Timing 3.3.9.1 Delta-Sigma Demodulator Digital Interface Timing The following parameters are applicable for the digital interface of the Delta-Sigma Demodulator (DSD). The data timing is relative to the active clock edge. Depending on the operation mode of the connected modulator that can be the rising and falling clock edge. Note: These parameters are not subject to production test, but verified by design and/or characterization. Table 43 DSD Interface Timing Parameters Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. MCLK period in master mode t 1 CC 33.3 – – ns t 1 ≥ 4x tPERIPH 1) 1) t PERIPH =1 / fPERIPH MCLK high time in master mode t 2 CC 9 – – ns t 2 > tPERIPH 1) MCLK low time in master mode t 3 CC 9 – – ns t 3 > tPERIPH 1) MCLK period in slave mode t 1 SR 33.3 – – ns t 1 ≥ 4x tPERIPH 1) MCLK high time in slave mode t 2 SR t PERIPH –– ns 1) MCLK low time in slave mode t 3 SR t PERIPH –– ns 1) DIN input setup time to the active clock edge t 4 SR t PERIPH +4 –– ns 1) DIN input hold time from the active clock edge t 5 SR t PERIPH +3 –– ns 1) Subject to Agreement on the Use of Product Information |
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