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S3C7565 Datasheet(PDF) 6 Page - Samsung semiconductor

Part No. S3C7565
Description  single-chip CMOS microcontroller
Download  42 Pages
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Maker  SAMSUNG [Samsung semiconductor]
Homepage  http://www.samsung.com/Products/Semiconductor
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S3C7565 Datasheet(HTML) 6 Page - Samsung semiconductor

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PRODUCT OVERVIEW
S3C7565/P7565
1-6
Table 1-1. S3C7565 Pin Descriptions (Continued)
Pin Name
Pin Type
Description
Share Pin
SI
I/O
Serial data input.
P0.2/K2
BUZ
I/O
0.5, 1, 2, or 4 kHz frequency output for buzzer sound.
P0.3/K3
INT0, INT1
I
External interrupts. The triggering edge for INT0 and
INT1 is selectable.
P1.0, P1.1
INT2
I
Quasi-interrupt with detection of rising or falling edges.
P1.2
INT4
I
External interrupt with a detection of rising and falling
edge.
P1.3
CLO
I/O
Clock output .
P2.0
TCLO0
I/O
Timer/counter 0 clock output.
P3.0
TCLO1
I/O
Timer/counter 1 clock output.
P3.1
TCL0
I/O
External clock input for timer/counter 0.
P3.2
TCL1
I/O
External clock input for timer/counter 1.
P3.3
CIN0
CIN1
CIN2
CIN3
I/O
4-Channel comparator input
CIN0–CIN2: comparator input only
CIN3: comparator input or external reference input
P7.0/SEG55
P7.1/SEG54
P7.2/SEG53
P7.3/SEG52
DTMF
O
DTMF output
LCDCK
I/O
LCD clock output
P8.0/SEG51
LCDSY
I/O
LCD synchronization clock output.
P8.1/SEG50
COM0–COM7
O
LCD common signal output.
COM8–COM11
I/O
P4.0–P4.3
COM12–COM15
P5.0–P5.3
SEG0–SEG39
O
LCD segment signal output.
SEG40–SEG59
I/O
P10.3–P6.0
K0–K3
I/O
External interrupt (triggering edge is selectable)
P0.0–P0.3
K4–K7
P6.0–P6.3
V
DD
Main power supply.
V
SS
Ground.
RESET
I
Reset signal.
V
LC1
LCD power supply.
P2.1
X
IN, XOUT
Crystal, Ceramic or RC oscillator pins for system clock.
XT
IN, XTOUT
Crystal oscillator pins for subsystem clock.
TEST
I
Chip test input pin.
Hold GND when the device is operating.
NOTE: Pull-up resistors for all I/O ports are automatically disabled if they are configured to output mode.


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